Clock Generator with Dual PLLs

GENERAL DESCRIPTION The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequ

文件：672.93 Kbytes 頁數(shù)：44 Pages

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Clock Generator with Dual PLLs, Spread Spectrum, and Margining

文件：746.39 Kbytes 頁數(shù)：44 Pages

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帶雙路PLL、擴(kuò)頻和余量微調(diào)功能的時鐘發(fā)生器

AD9577既提供一個多路輸出時鐘發(fā)生器功能，又帶有兩個片上鎖相環(huán)內(nèi)核PLL1和PLL2，專門針對網(wǎng)絡(luò)時鐘應(yīng)用而優(yōu)化。PLL設(shè)計基于ADI公司成熟的高性能、低抖動頻率合成器產(chǎn)品系列，確保實現(xiàn)較高的網(wǎng)絡(luò)性能。PLL具有I2C 可編程輸出頻率和格式。小數(shù)N分頻PLL可支持?jǐn)U頻時鐘功能，降低EMI輻射的峰值功率。兩個PLL均可支持頻率余量微調(diào)功能。 第一個整數(shù)N分頻PLL部分(PLL1)由一個鑒頻鑒相器(PFD)、一個電荷泵(CP)、一個低噪聲電壓控制振蕩器(VCO)、一個可編程反饋分頻器和兩個獨(dú)立可編程輸出分頻器組成。通過將外部晶振或基準(zhǔn)時鐘連接至REFCLK引腳，可將最高達(dá)637.5 ? 完全集成雙路PLL/VCO內(nèi)核 \n\n? 1個整數(shù)N分頻和1個小數(shù)N分頻PLL \n\n? 連續(xù)頻率范圍：11.2 MHz至200 MHz\n-- 提供200 MHz至637.5 MHz的大多數(shù)頻率\n\n? PLL1相位抖動\n（12 kHz至20 MHz）:\n460 fs rms（典型值）\n\n? PLL2相位抖動（12 kHz至20 MHz）\n- 整數(shù)N分頻模式:470 fs rms（典型值）\n- 小數(shù)N分頻模式:660 fs rms（典型值）;

ADI

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Clock Generator with Dual PLLs

GENERAL DESCRIPTION The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequ

文件：672.93 Kbytes 頁數(shù)：44 Pages

AD

亞德諾

Clock Generator with Dual PLLs

GENERAL DESCRIPTION The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequ

文件：672.93 Kbytes 頁數(shù)：44 Pages

AD

亞德諾

Clock Generator with Dual PLLs

GENERAL DESCRIPTION The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequ

文件：672.93 Kbytes 頁數(shù)：44 Pages

AD

亞德諾

Clock Generator with Dual PLLs

GENERAL DESCRIPTION The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequ

文件：672.93 Kbytes 頁數(shù)：44 Pages

AD

亞德諾

Clock Generator with Dual PLLs, Spread Spectrum, and Margining

文件：746.39 Kbytes 頁數(shù)：44 Pages

AD

亞德諾

Clock Generator with Dual PLLs, Spread Spectrum, and Margining

文件：746.39 Kbytes 頁數(shù)：44 Pages

AD

亞德諾

Clock Generator with Dual PLLs, Spread Spectrum, and Margining

文件：746.39 Kbytes 頁數(shù)：44 Pages

AD

亞德諾