1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 頁數(shù)：60 Pages

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包裝：散裝 功能：時鐘分配 類別：開發(fā)板，套件，編程器 評估和演示板及套件 描述：BOARD EVALUATION FOR AD9510

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1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 頁數(shù)：60 Pages

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亞德諾

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 頁數(shù)：60 Pages

AD

亞德諾

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 頁數(shù)：60 Pages

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亞德諾