800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

GENERAL DESCRIPTION The AD9513 features a three-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. FEATURES 1.6 GHz dif

文件：609.57 Kbytes 頁數(shù)：28 Pages

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800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outp

文件：481.09 Kbytes 頁數(shù)：28 Pages

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800 MHz時鐘分配IC，分頻器，延遲調(diào)整，三路輸出

AD9513是一款三路輸出時鐘分配IC，其低抖動和低相位噪聲特性能夠?qū)崿F(xiàn)優(yōu)質(zhì)的數(shù)據(jù)轉(zhuǎn)換器性能。這款器件也適合于對相位噪聲和抖動有嚴(yán)格要求的其它應(yīng)用。\n\n 三路獨(dú)立的時鐘輸出可被設(shè)置為LVDS或CMOS電平。在LVDS模式下，輸出工作在800 MHz；在CMOS模式下，輸出工作在250 MHz。\n\n 每路輸出都具有可編程的分頻器，可設(shè)置1~32的整數(shù)分頻比。一路時鐘輸出相對于其它時鐘輸出的相位可通過分頻器相位選擇功能進(jìn)行設(shè)置，用作時序粗調(diào)。\n\n 其中一路輸出提供延遲單元，具有3個可選擇的滿量程延遲值（1.5 ns、5 ns及10 ns），均可提供16級精 ? 1.6 GHz差分時鐘輸入\n\n? 3個可編程分頻器\n\n? 編程范圍：1至32\n\n? 用于延遲粗調(diào)的相位選擇\n\n? 節(jié)省空間的32引腳LFCSP封裝;

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800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

GENERAL DESCRIPTION The AD9513 features a three-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. FEATURES 1.6 GHz dif

文件：609.57 Kbytes 頁數(shù)：28 Pages

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800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

GENERAL DESCRIPTION The AD9513 features a three-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. FEATURES 1.6 GHz dif

文件：609.57 Kbytes 頁數(shù)：28 Pages

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亞德諾

800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

GENERAL DESCRIPTION The AD9513 features a three-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. FEATURES 1.6 GHz dif

文件：609.57 Kbytes 頁數(shù)：28 Pages

AD

亞德諾

800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

GENERAL DESCRIPTION The AD9513 features a three-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. FEATURES 1.6 GHz dif

文件：609.57 Kbytes 頁數(shù)：28 Pages

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800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

GENERAL DESCRIPTION The AD9513 features a three-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. FEATURES 1.6 GHz dif

文件：609.57 Kbytes 頁數(shù)：28 Pages

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800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

文件：610.35 Kbytes 頁數(shù)：28 Pages

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800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outp

文件：481.09 Kbytes 頁數(shù)：28 Pages

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