1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. FEATURES 1.6 GHz differ

文件：656.95 Kbytes 頁(yè)數(shù)：28 Pages

AD

亞德諾

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are two independe

文件：407.42 Kbytes 頁(yè)數(shù)：28 Pages

AD

亞德諾

Low Jitter Sampling Clock Generator for High Performance ADCs

文件：121.28 Kbytes 頁(yè)數(shù)：3 Pages

AD

亞德諾

1.6 GHz時(shí)鐘分配IC，分頻器，延遲調(diào)整，兩路輸出

AD9515是一款兩路輸出時(shí)鐘分配IC，具有低抖動(dòng)和低相位噪聲特性，有助于實(shí)現(xiàn)優(yōu)質(zhì)數(shù)據(jù)轉(zhuǎn)換器性能。這款器件也適合相位噪聲和抖動(dòng)要求嚴(yán)格的其它應(yīng)用。\n\n 它提供兩路獨(dú)立的時(shí)鐘輸出，一路輸出為L(zhǎng)VPECL，另一路輸出可以設(shè)置為L(zhǎng)VDS或CMOS電平。LVPECL輸出工作頻率為1.6 GHz。另一路輸出在LVDS模式下的工作頻率為800 MHz，在CMOS模式下的工作頻率為250 MHz。\n\n 每路輸出都具有可編程分頻器，可設(shè)置1至32的整數(shù)分頻比。一路時(shí)鐘輸出相對(duì)于其它時(shí)鐘輸出的相位可通過(guò)分頻器相位選擇功能進(jìn)行設(shè)置，用作時(shí)序粗調(diào)。\n\n LVDS/CMOS輸 ? 1.6 GHz 差分時(shí)鐘輸入 \n\n? 2 個(gè)可編程分頻器，編程范圍：\n1 至32 \n用于輸出到輸出延遲粗調(diào)的相位選擇 \n\n? 1.6 GHz LVPECL 時(shí)鐘輸出\nLVPECL加性輸出均方根抖動(dòng)：225 fs;

ADI

亞德諾

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. FEATURES 1.6 GHz differ

文件：656.95 Kbytes 頁(yè)數(shù)：28 Pages

AD

亞德諾

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are two independe

文件：407.42 Kbytes 頁(yè)數(shù)：28 Pages

AD

亞德諾

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are two independe

文件：407.42 Kbytes 頁(yè)數(shù)：28 Pages

AD

亞德諾

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are two independe

文件：407.42 Kbytes 頁(yè)數(shù)：28 Pages

AD

亞德諾

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. FEATURES 1.6 GHz differ

文件：656.95 Kbytes 頁(yè)數(shù)：28 Pages

AD

亞德諾

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. FEATURES 1.6 GHz differ

文件：656.95 Kbytes 頁(yè)數(shù)：28 Pages

AD

亞德諾