2-output 3.3V PCIe Zero-Delay Buffer

文件：300.42 Kbytes 頁(yè)數(shù)：19 Pages

IDT

2-output 3.3V PCIe Zero-Delay Buffer

文件：300.18 Kbytes 頁(yè)數(shù)：19 Pages

IDT

2-output 3.3V PCIe Zero-Delay Buffer

文件：300.42 Kbytes 頁(yè)數(shù)：19 Pages

IDT

2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator

文件：387.01 Kbytes 頁(yè)數(shù)：22 Pages

IDT

2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator

文件：387.01 Kbytes 頁(yè)數(shù)：22 Pages

IDT

2-output 3.3V PCIe Zero-Delay Buffer

文件：300.42 Kbytes 頁(yè)數(shù)：19 Pages

IDT

2-output 3.3V PCIe Zero-Delay Buffer

文件：300.42 Kbytes 頁(yè)數(shù)：19 Pages

IDT

2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer with Loss of Signal Indicator

The 9DBL0243 Zero-Delay/Fanout buffer is a low-power high-performance member of Reneas' Full-Featured PCIe family. The buffer supports PCIe Gen1–5 and provides a Loss of Signal (LOS) indicator. The device is an easy upgrade from the 9DBL0242. ? Loss of Signal (LOS) output; supports fault tolerant systems\n? Supports PCIe Gen1–5 CC and IR in fanout mode\n? Supports PCIe Gen1–5 CC in High Bandwidth ZDB mode\n? Direct connection to 100Ω transmission lines; saves 8 resistors compared to standard PCIe devices\n? Spread spectrum tolerant; allo;

Renesas

瑞薩

2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer

The 9DBL0252 2-output zero-delay/fan-out buffer is a 3.3V member of Renesas' Full-Featured PCIe family. The 9DBL0252 supports PCIe Gen1 through Gen5 and both Common and Independent Reference Clock architectures.\n\nFor information regarding evaluation boards and material, please contact your local?s ? Additive PCIe Gen5 CC jitter < 60fs RMS (fan-out mode)\n? 2 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair\n? Dedicated OE# pin for each output\n? Pin or SMBus configuration\n? SMBus interface not required for device operation\n? Space saving 24-pin 4 × 4 mm VFQFPN;

Renesas

瑞薩

2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer with Loss of Signal Indicator

The 9DBL0253 zero-delay/fanout buffer is a low-power high-performance member of Renesas' full-featured PCIe family. The buffer supports PCIe Gen 1–5 and provides a Loss of Signal (LOS) indicator. The device is an easy upgrade from the 9DBL0252.\nFor information regarding evaluation boards and materi ? Loss of Signal (LOS) output; supports fault tolerant systems\n? Supports PCIe Gen 1–5 CC in High Bandwidth Zero Delay Buffer (ZDB) mode\n? Spread spectrum tolerant; allows reduction of EMI\n? Easy AC coupling to other logic families; see application note AN-891.\n? Space saving 4mm × 4mm 24-VFQFPN;

Renesas

瑞薩