2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer with Loss of Signal Indicator

The 9DBL0253 zero-delay/fanout buffer is a low-power high-performance member of Renesas' full-featured PCIe family. The buffer supports PCIe Gen 1–5 and provides a Loss of Signal (LOS) indicator. The device is an easy upgrade from the 9DBL0252.\nFor information regarding evaluation boards and materi ? Loss of Signal (LOS) output; supports fault tolerant systems\n? Supports PCIe Gen 1–5 CC in High Bandwidth Zero Delay Buffer (ZDB) mode\n? Spread spectrum tolerant; allows reduction of EMI\n? Easy AC coupling to other logic families; see application note AN-891.\n? Space saving 4mm × 4mm 24-VFQFPN;

Renesas

瑞薩

2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers with LOS

Features ? LOS open-drain output indicates loss of input clock ? 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ? 9DBLxx4x devices provide integrated 100Ω terminations ? 9DBLxx5x devices provide integrated 85Ω terminations ? See AN-891 for easy coupling to othe

文件：1.36054 Mbytes 頁(yè)數(shù)：32 Pages

RENESAS

瑞薩

2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers with LOS

Features ? LOS open-drain output indicates loss of input clock ? 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ? 9DBLxx4x devices provide integrated 100Ω terminations ? 9DBLxx5x devices provide integrated 85Ω terminations ? See AN-891 for easy coupling to othe

文件：1.36054 Mbytes 頁(yè)數(shù)：32 Pages

RENESAS

瑞薩

2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator

文件：387.01 Kbytes 頁(yè)數(shù)：22 Pages

IDT

2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator

文件：387.01 Kbytes 頁(yè)數(shù)：22 Pages

IDT