2-output 3.3V PCIe Zero-Delay Buffer

文件：300.42 Kbytes 頁數(shù)：19 Pages

IDT

2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer

The 9DBL0252 2-output zero-delay/fan-out buffer is a 3.3V member of Renesas' Full-Featured PCIe family. The 9DBL0252 supports PCIe Gen1 through Gen5 and both Common and Independent Reference Clock architectures.\n\nFor information regarding evaluation boards and material, please contact your local?s ? Additive PCIe Gen5 CC jitter < 60fs RMS (fan-out mode)\n? 2 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair\n? Dedicated OE# pin for each output\n? Pin or SMBus configuration\n? SMBus interface not required for device operation\n? Space saving 24-pin 4 × 4 mm VFQFPN;

Renesas

瑞薩

2-output 3.3V PCIe Zero-Delay Buffer

文件：300.18 Kbytes 頁數(shù)：19 Pages

IDT

2-output 3.3V PCIe Zero-Delay Buffer

文件：300.42 Kbytes 頁數(shù)：19 Pages

IDT

2-output 3.3V PCIe Zero-Delay Buffer

文件：300.18 Kbytes 頁數(shù)：19 Pages

IDT

2-output 3.3V PCIe Zero-Delay Buffer

文件：300.42 Kbytes 頁數(shù)：19 Pages

IDT

Package：24-VFQFN 裸露焊盤；包裝：管件 類別：集成電路（IC） 應(yīng)用特定時鐘/定時 描述：CLOCK BUFFER 3.3V LP-HCSL PCIE

Renesas Electronics America Inc

Package：24-VFQFN 裸露焊盤；包裝：管件 類別：集成電路（IC） 應(yīng)用特定時鐘/定時 描述：VFQFPN 4.00X4.00X0.90 MM, 0.50MM

Renesas Electronics America Inc

Package：24-VFQFN 裸露焊盤；包裝：管件 類別：集成電路（IC） 應(yīng)用特定時鐘/定時 描述：VFQFPN 4.00X4.00X0.90 MM, 0.50MM

Renesas Electronics America Inc