| 型號 | 下載 訂購 | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
Electronic, 2 Pr #22 Str TC, PO Ins, 1Pr w/ TC Brd, PVC Jkt, CM Product Description Electronic, 2 Pair 22AWG (7x30) Tinned Copper, PO Insulation, 1 Pair w/ Tinned Copper Braid(62) Shield, PVC Outer Jacket, CM 文件：164.01 Kbytes 頁數(shù)：2 Pages | BELDEN 百通 | BELDEN | ||
Low Voltage, Low Skew 3.3V LVPECL Clock Generator Features ? Ten differential 3.3V LVPECL outputs ? Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL CLK1 inputs ? CLK0, nCLK0 supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? CLK1 accepts the following input levels: LVCMOS or LVTTL ? Maximum output frequency: 350MHz 文件：406.63 Kbytes 頁數(shù)：18 Pages | RENESAS 瑞薩 | RENESAS | ||
絲?。?a target="_blank" title="Marking" href="/87321ail/marking.html">87321AIL；Package：SOIC；÷1, ÷2 Differential-TO-LVPECL Clock Generator FEATURES ? One differential LVPECL output ? One CLK, nCLK input pair ? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? Maximum clock input frequency: 700MHz ? Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels 文件：521.919 Kbytes 頁數(shù)：19 Pages | RENESAS 瑞薩 | RENESAS | ||
絲?。?a target="_blank" title="Marking" href="/87321ail/marking.html">87321AIL；Package：SOIC；÷1, ÷2 Differential-TO-LVPECL Clock Generator FEATURES ? One differential LVPECL output ? One CLK, nCLK input pair ? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? Maximum clock input frequency: 700MHz ? Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels 文件：521.919 Kbytes 頁數(shù)：19 Pages | RENESAS 瑞薩 | RENESAS | ||
÷1, ÷2 Differential-TO-LVPECL Clock Generator FEATURES ? One differential LVPECL output ? One CLK, nCLK input pair ? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? Maximum clock input frequency: 700MHz ? Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels 文件：521.919 Kbytes 頁數(shù)：19 Pages | RENESAS 瑞薩 | RENESAS | ||
Low Skew, ÷1/÷2, 3.3V LVPECL/ECL Clock Generator FEATURES ? Fifteen differential LVPECL outputs ? Selectable LVPECL differential clock inputs ? CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL ? Output frequency: 750MHz (maximum) ? Output skew: 180ps (maximum) ? Bank skew: 65ps (maxi 文件：429.9 Kbytes 頁數(shù)：17 Pages | RENESAS 瑞薩 | RENESAS | ||
絲印：ICS87322BYILF；Package：LQFP；Low Skew, ÷1/÷2, 3.3V LVPECL/ECL Clock Generator FEATURES ? Fifteen differential LVPECL outputs ? Selectable LVPECL differential clock inputs ? CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL ? Output frequency: 750MHz (maximum) ? Output skew: 180ps (maximum) ? Bank skew: 65ps (maxi 文件：429.9 Kbytes 頁數(shù)：17 Pages | RENESAS 瑞薩 | RENESAS | ||
絲?。?a target="_blank" title="Marking" href="/ics87322byilf/marking.html">ICS87322BYILF；Package：LQFP；Low Skew, ÷1/÷2, 3.3V LVPECL/ECL Clock Generator FEATURES ? Fifteen differential LVPECL outputs ? Selectable LVPECL differential clock inputs ? CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL ? Output frequency: 750MHz (maximum) ? Output skew: 180ps (maximum) ? Bank skew: 65ps (maxi 文件：429.9 Kbytes 頁數(shù)：17 Pages | RENESAS 瑞薩 | RENESAS | ||
絲印：ICS8732AY-01LF；Package：LQFP；Low Voltage, Low Skew 3.3V LVPECL Clock Generator Features ? Ten differential 3.3V LVPECL outputs ? Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL CLK1 inputs ? CLK0, nCLK0 supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? CLK1 accepts the following input levels: LVCMOS or LVTTL ? Maximum output frequency: 350MHz 文件：406.63 Kbytes 頁數(shù)：18 Pages | RENESAS 瑞薩 | RENESAS | ||
絲?。?a target="_blank" title="Marking" href="/ics8732ay-01lf/marking.html">ICS8732AY-01LF；Package：LQFP；Low Voltage, Low Skew 3.3V LVPECL Clock Generator Features ? Ten differential 3.3V LVPECL outputs ? Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL CLK1 inputs ? CLK0, nCLK0 supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? CLK1 accepts the following input levels: LVCMOS or LVTTL ? Maximum output frequency: 350MHz 文件：406.63 Kbytes 頁數(shù)：18 Pages | RENESAS 瑞薩 | RENESAS |
技術參數(shù)
- 本體材質：
黃銅
- 本體鍍層：
錫
| 供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
Abbatron/HHSmith |
新 |
5 |
全新原裝 貨期兩周 |
詢價 | |||
Abbatron / HH Smith |
2022+ |
1 |
全新原裝 貨期兩周 |
詢價 | |||
24+ |
5000 |
公司存貨 |
詢價 | ||||
WINBOND |
2016+ |
TQFP100 |
9000 |
只做原裝,假一罰十,公司可開17%增值稅發(fā)票! |
詢價 | ||
WINBOND |
0716+P |
QFP128 |
2312 |
全新原裝 絕對有貨 |
詢價 | ||
HONEYWELL |
13+ |
DIP |
42448 |
原裝分銷 |
詢價 | ||
NS |
24+ |
QFP |
3500 |
原裝現(xiàn)貨,可開13%稅票 |
詢價 | ||
WINBOND |
25+ |
LQFP128 |
432 |
原裝現(xiàn)貨熱賣中,提供一站式真芯服務 |
詢價 | ||
AMIS |
24+ |
QFP100 |
25843 |
公司原廠原裝現(xiàn)貨假一罰十!特價出售!強勢庫存! |
詢價 | ||
TE |
16+ |
NA |
8800 |
原裝現(xiàn)貨,貨真價優(yōu) |
詢價 |
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