絲?。?a target="_blank" title="Marking" href="/ics85408bgilf/marking.html">ICS85408BGILF；Package：TSSOP；Low Skew, 1-to-8 , Different ial-to-LVDS Clock

文件：299.2 Kbytes 頁數(shù)：16 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/ics85408bgilf/marking.html">ICS85408BGILF；Package：TSSOP；Low Skew, 1-to-8 , Different ial-to-LVDS Clock

文件：299.2 Kbytes 頁數(shù)：16 Pages

IDT

絲印：ICS85408BGLF；Package：TSSOP；Low Skew, 1-to-8, Differential-to-LVDS Clock

文件：299.34 Kbytes 頁數(shù)：16 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/ics85408bglf/marking.html">ICS85408BGLF；Package：TSSOP；Low Skew, 1-to-8, Differential-to-LVDS Clock

文件：299.34 Kbytes 頁數(shù)：16 Pages

IDT

Low Skew, 1-to-8 , Different ial-to-LVDS Clock

文件：299.2 Kbytes 頁數(shù)：16 Pages

IDT

Low Skew,1-to-8,Differential-to-LVDS Clock

The 85408I is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip and a member of the family of High Performance Clock Solutions from IDT. The 85408I CLK, nCLK pair can accept most differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Vo ? Eight differential LVDS output pairs\n? CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\n? Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks\n? Multiple output enable inputs for disablin;

Renesas

瑞薩

Package：24-TSSOP（0.173"，4.40mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 時鐘緩沖器，驅(qū)動器 描述：IC CLK BUFFER 1:8 700MHZ 24TSSOP

Renesas Electronics America Inc