Low Skew, 1-to-8, Differential-to-LVDS Clock

Features ? Eight differential LVDS output pairs ? CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Maximum output frequency: 700MHz ? Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias netw

文件：539.82 Kbytes 頁數(shù)：17 Pages

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Low Skew,1-to-8,Differential-to-LVDS Clock

The 85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip from IDT. The 85408 CLK, nCLK pair can accept most differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the 85408 provides a low pow ? Eight differential LVDS output pairs\n? CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\n? Maximum output frequency: 700MHz\n? Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks\n? Transl;

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包裝：散裝 類別：標簽，標志，護欄，標識 標志，銘牌，招貼 描述：B302-10X14-YK-O-CAU-HAZARDOUS WA

Brady Corporation

包裝：散裝 類別：標簽，標志，護欄，標識 標志，銘牌，招貼 描述：B302-10X14-YK-O-CAU-HAZARDOUS WA

Brady Corporation

絲?。?a target="_blank" title="Marking" href="/ics85408bgilf/marking.html">ICS85408BGILF；Package：TSSOP；Low Skew, 1-to-8, Differential-to-LVDS Clock

Features ? Eight differential LVDS output pairs ? One differential clock input pair ? CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Maximum output frequency: 700MHz ? Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to

文件：635.03 Kbytes 頁數(shù)：17 Pages

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絲?。?a target="_blank" title="Marking" href="/ics85408bgilf/marking.html">ICS85408BGILF；Package：TSSOP；Low Skew, 1-to-8, Differential-to-LVDS Clock

Features ? Eight differential LVDS output pairs ? One differential clock input pair ? CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Maximum output frequency: 700MHz ? Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to

文件：635.03 Kbytes 頁數(shù)：17 Pages

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絲印：ICS85408BGLF；Package：TSSOP；Low Skew, 1-to-8, Differential-to-LVDS Clock

Features ? Eight differential LVDS output pairs ? CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Maximum output frequency: 700MHz ? Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias netw

文件：539.82 Kbytes 頁數(shù)：17 Pages

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絲印：ICS85408BGLF；Package：TSSOP；Low Skew, 1-to-8, Differential-to-LVDS Clock

Features ? Eight differential LVDS output pairs ? CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Maximum output frequency: 700MHz ? Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias netw

文件：539.82 Kbytes 頁數(shù)：17 Pages

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Low Skew, 1-to-8, Differential-to-LVDS Clock

Features ? Eight differential LVDS output pairs ? One differential clock input pair ? CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Maximum output frequency: 700MHz ? Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to

文件：635.03 Kbytes 頁數(shù)：17 Pages

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Low Skew, 1-to-8, Differential-to-LVDS Clock

文件：299.34 Kbytes 頁數(shù)：16 Pages

IDT