T1/E1 Interface Modules

文件：176.78 Kbytes 頁數(shù)：1 Pages

FILTRAN

費爾蘭特

Low Skew,1-to-9 Differential-to-HSTL Fanout Buffer

The 8521 is a low skew, 1-to-9 Differential-to-HSTL Fanout Buffer. The 8521 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to elimin 9 HSTL outputs\nSelectable differential CLK, nCLK or LVPECL clock inputs\nCLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL\nPCLK, nPCLK supports the following input types: LVPECL, CML, SSTL\nMaximum output frequency: 500MHz\nOutput skew: 50ps (maximum;

Renesas

瑞薩

絲印：8521；Package：SOT23-5；OPERATION INSTRUCTION

文件：1.97588 Mbytes 頁數(shù)：17 Pages

COREBAI

芯佰微

包裝：袋 類別：靜電控制，防靜電，ESD，無塵室產品 靜電控制器件容器，防靜電儀器盒子 描述：CARD CARRIER ESD SAFE 12X9X1.25\

Protektive Pak

COAXIAL CONNECTOR, SK, 50 Ohm, Straight cable plug (male)

Properties ? The shortened male pin ensures a non-destructive mating process ? Particularly well suited for semi-rigid, semi-flex and flexible cable ? Mechanical intermateable with SMA and PC 3.5 (3.5 mm standard)

文件：255.19 Kbytes 頁數(shù)：2 Pages

HUBERSUHNER

LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

GENERAL DESCRIPTION The ICS85211I is a low skew, high performance 1-to-2 Differential-to-LVHSTL Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels.The ICS85211I is characterized

文件：106.79 Kbytes 頁數(shù)：12 Pages

ICST

絲?。?a target="_blank" title="Marking" href="/211ai01l/marking.html">211AI01L；Package：SOIC；Low Skew, 1-to-2 Differential-to-HSTL Fanout Buffer

FEATURES ? Two differential HSTL compatible outputs ? One differential CLK, nCLK input pair ? CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCSL ? Maximum output frequency: 700MHz ? Translates any single-ended input signal to HSTL levels with r

文件：299.04 Kbytes 頁數(shù)：15 Pages

RENESAS

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絲印：211AI01L；Package：SOIC；Low Skew, 1-to-2 Differential-to-HSTL Fanout Buffer

FEATURES ? Two differential HSTL compatible outputs ? One differential CLK, nCLK input pair ? CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCSL ? Maximum output frequency: 700MHz ? Translates any single-ended input signal to HSTL levels with r

文件：299.04 Kbytes 頁數(shù)：15 Pages

RENESAS

瑞薩

Low Skew, 1-to-2, Differential-to-LVHSTL Fanout Buffer

Features ? Two differential LVHSTL compatible outputs ? One differential CLK, nCLK input pair ? CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL ? Maximum output frequency: 700MHz ? Translates any single ended input signal to LVHSTL levels w

文件：489.14 Kbytes 頁數(shù)：16 Pages

RENESAS

瑞薩

絲印：211BI03N；Package：SOIC；Low Skew, 1-to-2, Differential-to-LVHSTL Fanout Buffer

Features ? Two differential LVHSTL compatible outputs ? One differential CLK, nCLK input pair ? CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL ? Maximum output frequency: 700MHz ? Translates any single ended input signal to LVHSTL levels w

文件：489.14 Kbytes 頁數(shù)：16 Pages

RENESAS

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