8521中文資料Low Skew,1-to-9 Differential-to-HSTL Fanout Buffer數(shù)據(jù)手冊(cè)Renesas規(guī)格書(shū)

描述 Description

The 8521 is a low skew, 1-to-9 Differential-to-HSTL Fanout Buffer. The 8521 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output skew, part-to-part skew and crossover voltage characteristics make the 8521 ideal for today's most advanced applications, such as IA64 and static RAMs.

特性 Features

9 HSTL outputs
Selectable differential CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
Maximum output frequency: 500MHz
Output skew: 50ps (maximum)
Part-to-part skew: 250ps (maximum)
Propagation delay: 1.8ns (maximum)
VOH = 1.4V (maximum)
3.3V core, 1.8V output operating supply voltages
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request