Triple 3-input Positive NOR Gates

Triple 3-input Positive NOR Gates

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HITACHIHitachi Semiconductor

日立日立公司

TRIPLE 3-INPUT NOR GATE

TRIPLE 3-INPUT NOR GATE

文件：41.67 Kbytes 頁數(shù)：1 Pages

ETCList of Unclassifed Manufacturers

未分類制造商

Triple 3-input Positive NOR Gates

HITACHI

日立

OCTAL D FLIP-FLOP WITH CLEAR

The SN54/74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing. ? 8-Bit High Speed Register ? Parallel Register ? Commo

文件：184.87 Kbytes 頁數(shù)：5 Pages

MOTOROLA

摩托羅拉

OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP FLOP WITH RESET

文件：210.88 Kbytes 頁數(shù)：4 Pages

MITSUBISHI

三菱電機

8-Bit Register with Clear

General Description The DM74LS273 is a high speed 8-bit register, consisting of eight D-type flip-flops with a common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch row spacing. Features ■ Edge-triggered ■ 8-bit high speed regi

文件：66.92 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導體

LOW POWER SCHOTTKY

The SN74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing. ? 8-Bit High Speed Register ? Parallel Register ? Common C

文件：117.18 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導體

Octal D-type Positive-edge-triggered Flip-Flops(with Clear)

● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....)

文件：73.61 Kbytes 頁數(shù)：6 Pages

HITACHIHitachi Semiconductor

日立日立公司

Quadruple S-R Latches

Quadruple S-R Latches

文件：45.92 Kbytes 頁數(shù)：5 Pages

HITACHIHitachi Semiconductor

日立日立公司

Quad S-R Latch

General Description The DM74LS279 consists of four individual and independent Set-Reset Latches with active low inputs. Two of the four latches have an additional Sinput ANDed with the primary Sinput. A LOW on any Sinput while the Rinput is HIGH will be stored in the latch and appear on the corre

文件：47.44 Kbytes 頁數(shù)：4 Pages

FAIRCHILD

仙童半導體