絲?。?strong>74HC74D；Package：SOIC14；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description ? Dual D-Type Flip-Flop with Preset and Clear General The 74HC74D is a high speed CMOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The sign

文件：216.55 Kbytes 頁數(shù)：12 Pages

TOSHIBA

東芝

絲?。?strong>74HC74D；Package：SOIC14；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description ? Dual D-Type Flip-Flop with Preset and Clear General The 74HC74D is a high speed CMOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The sign

文件：216.55 Kbytes 頁數(shù)：12 Pages

TOSHIBA

東芝

Dual D-type flip-flop with set and reset; positive edge-trigger

General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HI

文件：175.47 Kbytes 頁數(shù)：21 Pages

恩XP

Dual D-type flip-flop with set and reset; positive edge-trigger

General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HI

文件：175.47 Kbytes 頁數(shù)：21 Pages

恩XP

Dual D Flip??lop with Set and Reset High??erformance Silicon??ate CMOS

The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip?flops with individual Set, Reset, and Clock inputs. Information at a D?input is transferred

文件：133.38 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導(dǎo)體

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Output capability: standard ? ICC category: flip-flops

文件：120.16 Kbytes 頁數(shù)：22 Pages

PHI

PHI

Dual D-type flip-flop with set and reset; positive edge-trigger

1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-

文件：299.12 Kbytes 頁數(shù)：19 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Output capability: standard ? ICC category: flip-flops

文件：120.16 Kbytes 頁數(shù)：22 Pages

PHI

PHI

Dual D-type flip-flop with set and reset; positive edge-trigger

General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HI

文件：175.47 Kbytes 頁數(shù)：21 Pages

恩XP

Dual D-type flip-flop with set and reset; positive edge-trigger

General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HI

文件：175.47 Kbytes 頁數(shù)：21 Pages

恩XP