Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Output capability: standard ? ICC category: flip-flops

文件：120.16 Kbytes 頁(yè)數(shù)：22 Pages

PHI

PHI

Dual D-type flip-flop with set and reset; positive edge-trigger

General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HI

文件：175.47 Kbytes 頁(yè)數(shù)：21 Pages

恩XP

Dual D-type flip-flop with set and reset; positive edge-trigger

General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HI

文件：175.47 Kbytes 頁(yè)數(shù)：21 Pages

恩XP

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：193.4 Kbytes 頁(yè)數(shù)：22 Pages

PHI

PHI

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：175.47 Kbytes 頁(yè)數(shù)：21 Pages

PHI

PHI

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：175.47 Kbytes 頁(yè)數(shù)：21 Pages

PHI

PHI

Dual D-type flip-flop with set and reset; positive edge-trigger

The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is ? Input levels:? For 74HC74: CMOS level\n? For 74HCT74: TTL level\n\n? Symmetrical output impedance\n? Low power dissipation\n? High noise immunity\n? Balanced propagation delays\n? Specified in compliance with JEDEC standard no. 7A\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A1;

Nexperia

安世

Package：14-SSOP（0.209"，5.30mm 寬）；包裝：卷帶（TR） 功能：設(shè)置（預(yù)設(shè)）和復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE DUAL 1BIT 14SSOP

Nexperia USA Inc.

Package：14-SSOP（0.209"，5.30mm 寬）；包裝：卷帶（TR） 功能：設(shè)置（預(yù)設(shè)）和復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE DUAL 1BIT 14SSOP

Nexperia USA Inc.