絲?。?strong>74HC259；Package：SO16；8-bit addressable latch

Features ? High speed: tPD = 20 ns (typ.) at VCC = 6 V ? Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C ? High noise immunity: VNIH = VNIL = 28 % VCC (min.) ? Symmetrical output impedance: |IOH| = IOL = 4 mA (min) ? Balanced propagation delays: tPLH ~= tPHL ? Wide operating volta

文件：684.36 Kbytes 頁數(shù)：19 Pages

STMICROELECTRONICS

意法半導(dǎo)體

絲印：74HC259D；Package：SOIC16；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description ? 8-Bit Addressable Latch General The 74HC259D is a high speed CMOS ADDRESSABLE LATCH fabricated with silicon gate C2MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The respective bits ar

文件：238.58 Kbytes 頁數(shù)：11 Pages

TOSHIBA

東芝

絲?。?a target="_blank" title="Marking" href="/74hc259y/marking.html">74HC259Y；Package：SO16(automotivegrade)；8-bit addressable latch

Features ? High speed: tPD = 20 ns (typ.) at VCC = 6 V ? Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C ? High noise immunity: VNIH = VNIL = 28 % VCC (min.) ? Symmetrical output impedance: |IOH| = IOL = 4 mA (min) ? Balanced propagation delays: tPLH ~= tPHL ? Wide operating volta

文件：684.36 Kbytes 頁數(shù)：19 Pages

STMICROELECTRONICS

意法半導(dǎo)體

絲?。?a target="_blank" title="Marking" href="/74hc259d/marking.html">74HC259D；Package：SOIC16；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description ? 8-Bit Addressable Latch General The 74HC259D is a high speed CMOS ADDRESSABLE LATCH fabricated with silicon gate C2MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The respective bits ar

文件：238.58 Kbytes 頁數(shù)：11 Pages

TOSHIBA

東芝

8-bit addressable latch

GENERAL DESCRIPTION The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Combines demultiplexer and 8-bit latch ? Serial-to-parallel capability ? Outp

文件：87.02 Kbytes 頁數(shù)：11 Pages

PHI

PHI

8-bit addressable latch

General description The 74HC259; 74HCT259 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A.

文件：134.88 Kbytes 頁數(shù)：21 Pages

恩XP

8-bit addressable latch

1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed l

文件：316.91 Kbytes 頁數(shù)：18 Pages

NEXPERIA

安世

8-bit addressable latch

General description The 74HC259; 74HCT259 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A.

文件：134.88 Kbytes 頁數(shù)：21 Pages

恩XP

8-bit addressable latch

1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed l

文件：316.91 Kbytes 頁數(shù)：18 Pages

NEXPERIA

安世

8-bit addressable latch

General description The 74HC259-Q100; 74HCT259-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.

文件：261.35 Kbytes 頁數(shù)：20 Pages

恩XP