Transceivers

74F641 Octal Bus Transceiver with Common Output Enable, Non-Inverting (Open Collector) 74F642 Octal Bus Transceiver with Common Output Enable, Inverting (Open Collector) FEATURES ? High-impedance NPN base inputs for reduced loading (20μA in High and Low states) ? Octal bidirectional bus in

文件：92.38 Kbytes 頁數：10 Pages

PHI

PHI

Transceivers

74F641 Octal Bus Transceiver with Common Output Enable, Non-Inverting (Open Collector) 74F642 Octal Bus Transceiver with Common Output Enable, Inverting (Open Collector) FEATURES ? High-impedance NPN base inputs for reduced loading (20μA in High and Low states) ? Octal bidirectional bus in

文件：92.38 Kbytes 頁數：10 Pages

PHI

PHI

Octal Bus Transceiver with 3-STATE Outputs

General Description These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA, have 3- STATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive (T

文件：54.69 Kbytes 頁數：6 Pages

FAIRCHILD

仙童半導體

Octal Bus Transceiver with 3-STATE Outputs

General Description These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA, have 3- STATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive (T

文件：54.69 Kbytes 頁數：6 Pages

FAIRCHILD

仙童半導體

Octal transceiver/register, non-inverting 3-State

DESCRIPTION The 74F646/74F646A and 74F648/74F648A transceivers/registers consist of bus transceiver circuits with 3–state outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus

文件：121.1 Kbytes 頁數：16 Pages

PHI

PHI

Octal Transceiver/Register with 3-STATE Outputs

General Description These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the a

文件：78.37 Kbytes 頁數：9 Pages

FAIRCHILD

仙童半導體

Octal transceiver/register, non-inverting 3-State

DESCRIPTION The 74F646/74F646A and 74F648/74F648A transceivers/registers consist of bus transceiver circuits with 3–state outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus

文件：121.1 Kbytes 頁數：16 Pages

PHI

PHI

Octal Transceiver/Register with 3-STATE Outputs

General Description These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the a

文件：78.37 Kbytes 頁數：9 Pages

FAIRCHILD

仙童半導體

Octal Transceiver/Register with 3-STATE Outputs

General Description These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the a

文件：78.37 Kbytes 頁數：9 Pages

FAIRCHILD

仙童半導體

Octal Transceiver/Register with 3-STATE Outputs

General Description These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the a

文件：78.37 Kbytes 頁數：9 Pages

FAIRCHILD

仙童半導體