| 型號 | 下載 訂購 | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
Octal D-Type Flip-Flop with 3-STATE Outputs General Description The 74F374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flipflops. Features ■ Edge-triggered D-type input 文件：67.57 Kbytes 頁數(shù)：7 Pages | FAIRCHILD 仙童半導(dǎo)體 | FAIRCHILD | ||
Octal D-Type Flip-Flop with 3-STATE Outputs General Description The 74F374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flipflops. Features ■ Edge-triggered D-type input 文件：67.57 Kbytes 頁數(shù)：7 Pages | FAIRCHILD 仙童半導(dǎo)體 | FAIRCHILD | ||
Octal D-Type Flip-Flop with 3-STATE Outputs General Description The 74F374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flipflops. Features ■ Edge-triggered D-type input 文件：67.57 Kbytes 頁數(shù)：7 Pages | FAIRCHILD 仙童半導(dǎo)體 | FAIRCHILD | ||
Octal D-Type Flip-Flop with Clock Enable General Description The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set 文件：62.13 Kbytes 頁數(shù)：6 Pages | FAIRCHILD 仙童半導(dǎo)體 | FAIRCHILD | ||
Octal D-type flip-flop with enable DESCRIPTION The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered. The state of each D input, one set-up time befor 文件：84.15 Kbytes 頁數(shù)：10 Pages | PHI PHI | PHI | ||
Octal D-Type Flip-Flop with Clock Enable General Description The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set 文件：62.13 Kbytes 頁數(shù)：6 Pages | FAIRCHILD 仙童半導(dǎo)體 | FAIRCHILD | ||
Octal D-Type Flip-Flop with Clock Enable General Description The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set 文件：62.13 Kbytes 頁數(shù)：6 Pages | FAIRCHILD 仙童半導(dǎo)體 | FAIRCHILD | ||
Octal D-Type Flip-Flop with Clock Enable General Description The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set 文件：62.13 Kbytes 頁數(shù)：6 Pages | FAIRCHILD 仙童半導(dǎo)體 | FAIRCHILD | ||
Parallel D-Type Register with Enable General Description The 74F378 is a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset. Features ■ 6-bit high-speed parallel register ■ Positive edge-triggered D-type inputs ■ Fully buffered common clock 文件：56.66 Kbytes 頁數(shù)：6 Pages | FAIRCHILD 仙童半導(dǎo)體 | FAIRCHILD | ||
Hex D flip-flop with enable DESCRIPTION The 74F378 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge-triggered. The state of each D input, one setup time befor 文件：81.68 Kbytes 頁數(shù)：10 Pages | PHI PHI | PHI |
技術(shù)參數(shù)
- 類型：
D 型
- 輸出類型：
三態(tài)，非反相
- 元件數(shù)：
1
- 每元件位數(shù)：
8
- 時鐘頻率：
140MHz
- 不同 V，最大 CL 時的最大傳播延遲：
8.5ns @ 5V，50pF
- 觸發(fā)器類型：
正邊沿
- 電流 - 輸出高，低：
3mA，24mA
- 電壓 - 電源：
4.5 V ~ 5.5 V
- 電流 - 靜態(tài)（Iq)：
86mA
- 工作溫度：
0°C ~ 70°C（TA）
- 安裝類型：
表面貼裝
- 封裝/外殼：
20-SOIC（0.295\，7.50mm 寬）
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
24+ |
5000 |
公司存貨 |
詢價 | ||||
NS |
24+ |
SOP5.2 |
6980 |
原裝現(xiàn)貨,可開13%稅票 |
詢價 | ||
MC |
23+ |
SOP14/5 |
8650 |
受權(quán)代理!全新原裝現(xiàn)貨特價熱賣! |
詢價 | ||
NATIONAL |
06+ |
原廠原裝 |
1051 |
只做全新原裝真實現(xiàn)貨供應(yīng) |
詢價 | ||
FSC |
13+ |
PDIP-20 |
1988 |
原裝分銷 |
詢價 | ||
NS |
DIP |
1000 |
原裝長期供貨! |
詢價 | |||
FAIR |
87+ |
DIP20 |
2760 |
全新原裝進口自己庫存優(yōu)勢 |
詢價 | ||
恩XP |
2016+ |
DIP |
3000 |
只做原裝,假一罰十,公司可開17%增值稅發(fā)票! |
詢價 | ||
FAIR |
24+ |
原廠封裝 |
8060 |
原裝現(xiàn)貨假一罰十 |
詢價 | ||
恩XP |
23+ |
SOP20 |
5000 |
原裝正品,假一罰十 |
詢價 |
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