Quad Two-Input NAND Buffer

General Description This device contains four independent gates, each of which performs the logic NAND function.

文件：48.89 Kbytes 頁數(shù)：4 Pages

FAIRCHILD

仙童半導(dǎo)體

Quad 2-input NAND buffer

Quad 2-input NAND buffer

文件：69.76 Kbytes 頁數(shù)：8 Pages

PHI

PHI

Quad 2-input NAND buffer

恩XP

Quad Two-Input NAND Buffer

ONSEMI

安森美半導(dǎo)體

Octal transparent latch 3-State

DESCRIPTION The 74F373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the enable (E) input is

文件：93.64 Kbytes 頁數(shù)：12 Pages

PHI

PHI

Latch/flip-flop

FEATURES ? 8-bit transparent latch — 74F373 ? 8-bit positive edge triggered register — 74F374 ? 3-State outputs glitch free during power-up and power-down ? Common 3-State output register ? Independent register and 3-State buffer operation ? SSOP Type II Package DESCRIPTION The 74F373 is a

文件：268.67 Kbytes 頁數(shù)：14 Pages

NEXPERIA

安世

Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

文件：79.76 Kbytes 頁數(shù)：8 Pages

FAIRCHILD

仙童半導(dǎo)體

Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

文件：79.76 Kbytes 頁數(shù)：8 Pages

FAIRCHILD

仙童半導(dǎo)體

74F373 Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

文件：80.81 Kbytes 頁數(shù)：8 Pages

FAIRCHILD

仙童半導(dǎo)體

74F373 Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

文件：80.81 Kbytes 頁數(shù)：8 Pages

FAIRCHILD

仙童半導(dǎo)體