CMOS Dual 4-Stage Static Shift Register

文件：229.06 Kbytes 頁數(shù)：8 Pages

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CMOS Dual 4-Stage Static Shift Register

文件：229.06 Kbytes 頁數(shù)：8 Pages

UTC

友順

CMOS Dual 4-Stage Static Shift Register

文件：229.06 Kbytes 頁數(shù)：8 Pages

UTC

友順

CMOS DUAL 4-STAGE STATIC SHIFT REGISTER

UCD4015B consists of two identical,independent,4-stageserial-input/parallel-output registers. Each register has independent CLOCK and RESET input as well as a single serial DATA input. ”Q” outputs are available from each of the four stages on both registers. All registers stages are D-type,master-sl ? 12MHz (typ.) clock rate at 10V \n? Maximum input current of 1μA at 18V \n? Fully static operation \n? 8 master-slave flip-flops plus input and output buffering;

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