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首頁 >UCA6472N>規(guī)格書列表

型號	下載訂購	功能描述	制造商上傳企業(yè)	LOGO
UCA6472N	文件：1.62317 Mbytes Page：29 Pages	UCY74 and UCA64 Series 文件：1.62317 Mbytes 頁數(shù)：29 Pages	ETCList of Unclassifed Manufacturers 未分類制造商	ETC
UCA6472N	文件：232.63 Kbytes Page：4 Pages	UKLAD SCALONY CYFROWY 文件：232.63 Kbytes 頁數(shù)：4 Pages	ETCList of Unclassifed Manufacturers 未分類制造商	ETC
6472	文件：38.72 Kbytes Page：1 Pages	SMD Microtip Test Probe Set 文件：38.72 Kbytes 頁數(shù)：1 Pages	POMONA Pomona Electronics	POMONA
AD6472	文件：114.03 Kbytes Page：8 Pages	2 Pair/1 Pair ETSI Compatible HDSL Analog Front End GENERAL DESCRIPTION The AD6472 is a single chip analog front end for two pair or single pair HDSL applications that use 1168 Kbps or 2.32 Mbps data rates. The AD6472 integrates all the transmit and receive functional blocks together with the timing recovery DAC. The digital interface is desi 文件：114.03 Kbytes 頁數(shù)：8 Pages	AD 亞德諾	AD
AD6472BS	文件：114.03 Kbytes Page：8 Pages	2 Pair/1 Pair ETSI Compatible HDSL Analog Front End GENERAL DESCRIPTION The AD6472 is a single chip analog front end for two pair or single pair HDSL applications that use 1168 Kbps or 2.32 Mbps data rates. The AD6472 integrates all the transmit and receive functional blocks together with the timing recovery DAC. The digital interface is desi 文件：114.03 Kbytes 頁數(shù)：8 Pages	AD 亞德諾	AD

更多UCA6472N供應商更新時間2026-1-22 16:01:00