2 Pair/1 Pair ETSI Compatible HDSL Analog Front End

GENERAL DESCRIPTION The AD6472 is a single chip analog front end for two pair or single pair HDSL applications that use 1168 Kbps or 2.32 Mbps data rates. The AD6472 integrates all the transmit and receive functional blocks together with the timing recovery DAC. The digital interface is desi

文件：114.03 Kbytes 頁(yè)數(shù)：8 Pages

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2 Pair/1 Pair ETSI Compatible HDSL Analog Front End

GENERAL DESCRIPTION\nThe AD6472 is a single chip analog front end for two pair or single pair HDSL applications that use 1168 Kbps or 2.32 Mbps data rates.\nThe AD6472 integrates all the transmit and receive functional blocks together with the timing recovery DAC. The digital interface is designed t Integrated Front End for Single Pair or Two Pair HDSL Systems\nMeets ETSI Specifications\nSupports 1168 Kbps and 2.32 Mbps\nTransmit and Receive Signal Path Functions\n? Receive Hybrid Amplifier, PGA and ADC\n? Transmit DAC, Filter and Differential Outputs\n? Programmable Filters\nControl and Ancill;

ADI

亞德諾

2 Pair/1 Pair ETSI Compatible HDSL Analog Front End

GENERAL DESCRIPTION The AD6472 is a single chip analog front end for two pair or single pair HDSL applications that use 1168 Kbps or 2.32 Mbps data rates. The AD6472 integrates all the transmit and receive functional blocks together with the timing recovery DAC. The digital interface is desi

文件：114.03 Kbytes 頁(yè)數(shù)：8 Pages

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