P-Channel Enhancement-Mode Vertical DMOS FET

General Description This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high inpu

文件：697.33 Kbytes 頁數(shù)：5 Pages

SUTEX

P-Channel Enhancement-Mode Vertical DMOS FETs

General Description This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high inpu

文件：480.47 Kbytes 頁數(shù)：4 Pages

SUTEX

P-Channel Enhancement-Mode Vertical DMOS FET

文件：311.77 Kbytes 頁數(shù)：14 Pages

MICROCHIP

微芯科技

P-Channel Enhancement-Mode Vertical DMOS FET

General Description\nThis? low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input im ?Lowthreshold (-2.4V max.)\n?High input impedance\n?Low input capacitance (95pF typical)\n?Fast switching speeds\n?Low on-resistance\n?Free from secondary breakdown\n?Low input and output leakageApplications\n?Logic level interfaces - ideal for TTL and CMOS\n?Solid state relays\n?Battery operated sy;

Microchip

微芯科技

P-Channel Enhancement-Mode Vertical DMOS FETs

Low Threshold DMOS Technology\nThese low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex's well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the h ? Low threshold — -2.4V max.\n? High input impedance\n? Low input capacitance — 95pF typical\n? Fast switching speeds\n? Low on resistance\n? Free from secondary breakdown\n? Low input and output leakage\n? Complementary N- and P-channel devicesApplications\n? Logic level interfaces – ideal for TTL ;

Microchip

微芯科技