Galvanically isolated 3 A single gate driver for Enhancement mode GaN FETs

Features ? High voltage rail up to 1200 V ? Driver current capability: 2 A / 3 A source/sink @25 °C, VH = 6 V ? dV/dt transient immunity ±100 V/ns ? Input-output propagation delay: 45 ns ? Separate sink and source option for easy gate driving configuration ? UVLO function optimized for GaN

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絲?。?a target="_blank" title="Marking" href="/gap2gs/marking.html">GAP2GS；Package：SO-8；Galvanically isolated 3 A single gate driver for Enhancement mode GaN FETs

Features ? High voltage rail up to 1200 V ? Driver current capability: 2 A / 3 A source/sink @25 °C, VH = 6 V ? dV/dt transient immunity ±100 V/ns ? Input-output propagation delay: 45 ns ? Separate sink and source option for easy gate driving configuration ? UVLO function optimized for GaN

文件：551.02 Kbytes 頁數(shù)：20 Pages

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絲印：GAP2GS；Package：SO-8；Galvanically isolated 3 A single gate driver for Enhancement mode GaN FETs

Features ? High voltage rail up to 1200 V ? Driver current capability: 2 A / 3 A source/sink @25 °C, VH = 6 V ? dV/dt transient immunity ±100 V/ns ? Input-output propagation delay: 45 ns ? Separate sink and source option for easy gate driving configuration ? UVLO function optimized for GaN

文件：551.02 Kbytes 頁數(shù)：20 Pages

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Isolated 3 A single gate driver for Enhancement mode GaN FETs

Features ? High voltage rail up to 1700 V ? Driver current capability: 2 A / 3 A source/sink @25 °C, VH = 6 V ? dV/dt transient immunity ±100 V/ns ? Input-output propagation delay: 45 ns ? Separate sink and source option for easy gate driving configuration ? UVLO function optimized for GaN

文件：556.07 Kbytes 頁數(shù)：20 Pages

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絲?。?a target="_blank" title="Marking" href="/gap2gsn/marking.html">GAP2GSN；Package：SO-8；Isolated 3 A single gate driver for Enhancement mode GaN FETs

Features ? High voltage rail up to 1700 V ? Driver current capability: 2 A / 3 A source/sink @25 °C, VH = 6 V ? dV/dt transient immunity ±100 V/ns ? Input-output propagation delay: 45 ns ? Separate sink and source option for easy gate driving configuration ? UVLO function optimized for GaN

文件：556.07 Kbytes 頁數(shù)：20 Pages

STMICROELECTRONICS

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絲?。?a target="_blank" title="Marking" href="/gap2gsn/marking.html">GAP2GSN；Package：SO-8；Isolated 3 A single gate driver for Enhancement mode GaN FETs

Features ? High voltage rail up to 1700 V ? Driver current capability: 2 A / 3 A source/sink @25 °C, VH = 6 V ? dV/dt transient immunity ±100 V/ns ? Input-output propagation delay: 45 ns ? Separate sink and source option for easy gate driving configuration ? UVLO function optimized for GaN

文件：556.07 Kbytes 頁數(shù)：20 Pages

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電氣隔離3 A單柵極驅(qū)動器，用于增強模式GaN FET

STGAP2GS是在柵極驅(qū)動通道與低壓控制和接口電路之間提供電流隔離的單柵極驅(qū)動器。\n\n 該柵極驅(qū)動器具有2 A供電電流、3 A受電電流和軌到軌輸出，使得該器件同樣適用于工業(yè)應(yīng)用中的功率轉(zhuǎn)換、電機驅(qū)動逆變器等高功率應(yīng)用。\n\n 該器件可以通過專用柵極電阻進行獨立的導(dǎo)通和關(guān)斷優(yōu)化。\n\n 該器件集成了多種保護功能，包括熱關(guān)斷和UVLO，這些功能針對增強模式GaN FET進行了優(yōu)化，可輕松幫助用戶設(shè)計出高效可靠的系統(tǒng)。雙輸入引腳允許選擇信號極性控制和實現(xiàn)HW聯(lián)鎖保護，以避免在控制器故障時發(fā)生交叉?zhèn)鲗?dǎo)。\n\n 輸入到輸出的傳播延遲在45 ns內(nèi)，PWM控制精度高。\n\n 可以使用待機模式 ? 高壓導(dǎo)軌達1200 V \n? 驅(qū)動器電流能力：25 ℃條件下，2A/3A供電/受電電流，VH = 6 V \n? dV/dt瞬態(tài)抗擾度±100 V/ns \n? 輸入到輸出的傳播延遲：45 ns \n? 獨立的電流拉灌選項，輕松實現(xiàn)柵極驅(qū)動配置 \n? UVLO功能針對GaN進行優(yōu)化? 柵極驅(qū)動電壓高達15 V \n? 具有遲滯的3.3 V、5 V TTL/CMOS輸入 \n? 溫度關(guān)斷保護 \n? 待機功能 \n? 寬體SO-8W封裝;

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Isolated 3 A single gate driver for Enhancement mode GaN FETs

The STGAP2GSN is a single gate driver which provides isolation between the gate driving channel and the low voltage control and interface circuitry.\n\n The gate driver is characterized by 2 A source and 3 A sink capability and rail-to-rail outputs, making the device also suitable for mid and high p ? High voltage rail up to 1700 V \n? Driver current capability: 2 A / 3 A source/sink @25 °C, VH = 6 V \n? dV/dt transient immunity ±100 V/ns \n? Input-output propagation delay: 45 ns \n? Separate sink and source option for easy gate driving configuration \n? UVLO function optimized for GaN? Gate dr;

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意法半導(dǎo)體