| 型號 | 下載 訂購 | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
絲?。?a target="_blank" title="Marking" href="/sn74ls374n/marking.html">SN74LS374N；Package：PDIP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲印：74LS374；Package：SOP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an 文件：395.7 Kbytes 頁數(shù)：9 Pages | TI 德州儀器 | TI | ||
4-BIT D LATCH The SN54/74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follo 文件：163.97 Kbytes 頁數(shù)：5 Pages | MOTOROLA 摩托羅拉 | MOTOROLA | ||
絲?。?a target="_blank" title="Marking" href="/ls375/marking.html">LS375；Package：SOIC；4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an 文件：395.7 Kbytes 頁數(shù)：9 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/ls375/marking.html">LS375；Package：SOIC；4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an 文件：395.7 Kbytes 頁數(shù)：9 Pages | TI 德州儀器 | TI | ||
4-BIT D LATCH The SN54/74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follo 文件：163.97 Kbytes 頁數(shù)：5 Pages | MOTOROLA 摩托羅拉 | MOTOROLA | ||
絲?。?a target="_blank" title="Marking" href="/sn74ls375n/marking.html">SN74LS375N；Package：PDIP；4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an 文件：395.7 Kbytes 頁數(shù)：9 Pages | TI 德州儀器 | TI | ||
絲印：SN74LS375N；Package：PDIP；4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an 文件：395.7 Kbytes 頁數(shù)：9 Pages | TI 德州儀器 | TI | ||
LOW POWER SCHOTTKY The SN74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. ? 8-Bit High Speed Parallel Registers ? Positive Edge-Triggered D-Type Flip Flops ? F 文件：127.6 Kbytes 頁數(shù)：8 Pages | ONSEMI 安森美半導(dǎo)體 | ONSEMI |
替換型號
技術(shù)參數(shù)
- Supply voltage (Min) (V)：
4.75
- Supply voltage (Max) (V)：
5.25
- Number of channels (#)：
4
- Inputs per channel：
2
- IOL (Max) (mA)：
48
- IOH (Max) (mA)：
-1.2
- Input type：
Bipolar
- Output type：
Push-Pull
- Features：
High speed (tpd 10- 50ns)
- Data rate (Max) (Mbps)：
35
- Rating：
Catalog
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
TI德州儀器 |
22+ |
24000 |
原裝正品現(xiàn)貨,實單可談,量大價優(yōu) |
詢價 | |||
TI |
2015+ |
SOP |
19889 |
一級代理原裝現(xiàn)貨,特價熱賣! |
詢價 | ||
TI |
09+ |
SSOP20 |
5500 |
原裝無鉛,優(yōu)勢熱賣 |
詢價 | ||
TI |
24+ |
SOP5.2mm |
6868 |
原裝現(xiàn)貨,可開13%稅票 |
詢價 | ||
TI |
25+ |
SOP |
1100 |
強調(diào)現(xiàn)貨,隨時查詢! |
詢價 | ||
TI |
25+ |
DIP-20 |
18000 |
原廠直接發(fā)貨進(jìn)口原裝 |
詢價 | ||
TI |
5 |
240 |
正品原裝--自家現(xiàn)貨-實單可談 |
詢價 | |||
TI |
16+ |
DIP |
61 |
全新原裝現(xiàn)貨 |
詢價 | ||
TI |
2016+ |
SOP20 |
3900 |
只做原裝,假一罰十,公司可開17%增值稅發(fā)票! |
詢價 | ||
TI |
24+ |
原廠原封 |
6523 |
進(jìn)口原裝公司百分百現(xiàn)貨可出樣品 |
詢價 |
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