Monolithic Peak Detector with Reset-and-Hold Mode

GENERAL DESCRIPTION The PKD01 tracks an analog input signal until a maximum amplitude is reached. The maximum value is then retained as a peak voltage on a hold capacitor. Being a monolithic circuit, the PKD01 offers significant performance and package density advantages over hybrid modules and

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Monolithic Peak Detector with Reset-and-Hold Mode

GENERAL DESCRIPTION\nThe PKD01 tracks an analog input signal until a maximum amplitude is reached. The maximum value is then retained as a peak voltage on a hold capacitor. Being a monolithic circuit, the PKD01 offers significant performance and package density advantages over hybrid modules and dis Monolithic Design for Reliability and Low Cost\nHigh Slew Rate: 0.5 V/μs\nLow Droop Rate\n?? TA = 25°C: 0.1 mV/ms\n?? TA = 125°C: 10 mV/ms\nLow Zero-Scale Error: 4 mV\nDigitally Selected Hold and Reset Modes\nReset to Positive or Negative Voltage Levels\nLogic Signals TTL and CMOS Compatible\nUncomm;

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DIP18

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上傳：深圳市勝彬電子有限公司

最新

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上傳：君宇國際實業(yè)有限公司

GTR模塊

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上傳：深圳市華來深電子有限公司