絲?。?a target="_blank" title="Marking" href="/-7c/marking.html">-7C；Package：SOT-323；PNP resistor-equipped transistors; R1 = 100 kW, R2 = 100 kW

PNP resistor-equipped transistors; R1 = 100 k?, R2 = 100 k? DESCRIPTION PNP resistor-equipped transistor (see “Simplified outline, symbol and pinning” for package details). FEATURES ? Built-in bias resistors ? Simplified circuit design ? Reduction of component count ? Re

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PHI

PHI

絲?。?a target="_blank" title="Marking" href="/-7c/marking.html">-7C；Package：SOT-323；PNP resistor-equipped transistors; R1 = 100 k廓, R2 = 100 k廓

DESCRIPTION PNP resistor-equipped transistor (see “Simplified outline, symbol and pinning” for package details). FEATURES ? Built-in bias resistors ? Simplified circuit design ? Reduction of component count ? Reduced pick and place costs. APPLICATIONS ? General purpose switching and amplif

文件：189.96 Kbytes 頁數(shù)：14 Pages

恩XP

絲?。?a target="_blank" title="Marking" href="/00100000/marking.html">00100000；Package：SOT883B；PNP resistor-equipped transistor; R1 = 100 k廓, R2 = 100 k廓

文件：960.46 Kbytes 頁數(shù)：12 Pages

NEXPERIA

安世

絲印：WAB；Package：SOT-23；Low VCEsat (BISS) transistors

文件：948.33 Kbytes 頁數(shù)：12 Pages

PHI

PHI

絲?。?a target="_blank" title="Marking" href="/-7c/marking.html">-7C；Package：SOT-323；Low VCEsat (BISS) transistors

文件：948.33 Kbytes 頁數(shù)：12 Pages

PHI

PHI

PNP resistor-equipped transistors; R1 = 100 kΩ, R2 = 100 kΩ

DESCRIPTION\nPNP resistor-equipped transistor (see “Simplified outline, symbol and pinning” for package details).FEATURES\n? Built-in bias resistors\n? Simplified circuit design\n? Reduction of component count\n? Reduced pick and place costs.APPLICATIONS\n? General purpose switching and amplificatio ? Built-in bias resistors\n? Simplified circuit design\n? Reduction of component count\n? Reduced pick and place costs.;

恩XP

PNP resistor-equipped transistors; R1 = 100 kOhm, R2 = 100 kOhm

PNP resistor-equipped transistor (see ?Simplified outline, symbol and pinning? for package details). ? Built-in bias resistors\n? Simplified circuit design\n? Reduction of component count\n? Reduced pick and place costs.\n? AEC-Q101 qualified;

Nexperia

安世

PNP resistor-equipped transistor; R1 = 100 kΩ, R2 = 100 kΩ

PNP Resistor-Equipped Transistor (RET) in a leadless ultra small DFN1006B-3 (SOT883B) Surface-Mounted Device (SMD) plastic package. NPN complement: PDTC115EMB. ? 20 mA output current capability\n? Reduces component count\n? Built-in bias resistors\n? Reduces pick and place costs\n? Simplifies circuit design\n? AEC-Q101 qualified\n? Leadless ultra small SMD plastic package\n? Low package height of 0.37 mm;

Nexperia

安世

Package：3-XFDFN；包裝：卷帶（TR） 類別：分立半導(dǎo)體產(chǎn)品 晶體管 - 雙極（BJT）- 單，預(yù)偏置 描述：TRANS PREBIAS PNP 50V DFN1006B-3

Nexperia USA Inc.

Package：TO-236-3，SC-59，SOT-23-3；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：分立半導(dǎo)體產(chǎn)品 晶體管 - 雙極（BJT）- 單，預(yù)偏置 描述：TRANS PREBIAS PNP 50V TO236AB

Nexperia USA Inc.