PCF85xxC-2 family 256 to 1024 ? 8-bit CMOS EEPROMs with I2C-bus interface

文件：179.21 Kbytes 頁(yè)數(shù)：24 Pages

ICST

Bootable CPU RTC with two I2C buses, 128 byte SRAM and alarm function

1 General description The PCF85053A is a CMOS Real-Time Clock (RTC) and calendar optimized for low power consumption and automatic switching to battery on primary power loss. Featuring clock output, ALRT (interrupt) output and 128 bytes of battery backup SRAM. The PCF85053A includes two I2C buses

文件：662.96 Kbytes 頁(yè)數(shù)：43 Pages

恩XP

Bootable CPU RTC with two I2C buses, 128 byte SRAM and alarm function

Features and benefits ? Voltage range addresses common supply rails – VDD supply voltage from 1.7 V to 3.6 V – VBAT battery supply voltage from 1.55 V to 3.6 V ? Two independent I2C interfaces with up to 400 kHz speed – Primary I2C bus with Read/write capability on RTC and SRAM registers – S

文件：680.22 Kbytes 頁(yè)數(shù)：48 Pages

恩XP

Bootable CPU RTC with two I2C buses, 128 byte SRAM and alarm function

Features and benefits ? Voltage range addresses common supply rails – VDD supply voltage from 1.7 V to 3.6 V – VBAT battery supply voltage from 1.55 V to 3.6 V ? Two independent I2C interfaces with up to 400 kHz speed – Primary I2C bus with Read/write capability on RTC and SRAM registers – S

文件：680.22 Kbytes 頁(yè)數(shù)：48 Pages

恩XP

絲?。?a target="_blank" title="Marking" href="/85053/marking.html">85053；Package：HVSON12；Bootable CPU RTC with two I2C buses, 128 byte SRAM and alarm function

Features and benefits ? Voltage range addresses common supply rails – VDD supply voltage from 1.7 V to 3.6 V – VBAT battery supply voltage from 1.55 V to 3.6 V ? Two independent I2C interfaces with up to 400 kHz speed – Primary I2C bus with Read/write capability on RTC and SRAM registers – S

文件：680.22 Kbytes 頁(yè)數(shù)：48 Pages

恩XP

絲印：85053；Package：HVSON12；Bootable CPU RTC with two I2C buses, 128 byte SRAM and alarm function

1 General description The PCF85053A is a CMOS Real-Time Clock (RTC) and calendar optimized for low power consumption and automatic switching to battery on primary power loss. Featuring clock output, ALRT (interrupt) output and 128 bytes of battery backup SRAM. The PCF85053A includes two I2C buses

文件：662.96 Kbytes 頁(yè)數(shù)：43 Pages

恩XP

Bootable CPU RTC with two I2C buses, 128 byte SRAM and alarm function

1 General description The PCF85053A is a CMOS Real-Time Clock (RTC) and calendar optimized for low power consumption and automatic switching to battery on primary power loss. Featuring clock output, ALRT (interrupt) output and 128 bytes of battery backup SRAM. The PCF85053A includes two I2C buses

文件：662.96 Kbytes 頁(yè)數(shù)：43 Pages

恩XP

Bootable CPU RTC with two I2C buses, 128 byte SRAM and alarm function

Features and benefits ? Voltage range addresses common supply rails – VDD supply voltage from 1.7 V to 3.6 V – VBAT battery supply voltage from 1.55 V to 3.6 V ? Two independent I2C interfaces with up to 400 kHz speed – Primary I2C bus with Read/write capability on RTC and SRAM registers – S

文件：680.22 Kbytes 頁(yè)數(shù)：48 Pages

恩XP

Tiny Real-Time Clock/calendar with alarm function and I2C-bus

1 General description The PCF85063A is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power consumption. An offset register allows fine-tuning of the clock. All addresses and data are transferred serially via the two-line bidirectional I2C-bus. Maximum data rate is 400 kbit/s. The

文件：698.92 Kbytes 頁(yè)數(shù)：55 Pages

恩XP

Tiny Real-Time Clock/calendar with alarm function and I2C-bus

1 General description The PCF85063A is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power consumption. An offset register allows fine-tuning of the clock. All addresses and data are transferred serially via the two-line bidirectional I2C-bus. Maximum data rate is 400 kbit/s. The

文件：698.92 Kbytes 頁(yè)數(shù)：55 Pages

恩XP