Octal registered transceiver with parity and flags 3-State

DESCRIPTION The 74F522 Octal Registered Transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock (CPR, CPS) and Clock Enable (CER, CES) inputs, as well as a flag flip-flop that is set automatically as the register is lo

文件：115.12 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Octal registered transceiver with parity and flags 3-State

DESCRIPTION The 74F522 Octal Registered Transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock (CPR, CPS) and Clock Enable (CER, CES) inputs, as well as a flag flip-flop that is set automatically as the register is lo

文件：115.12 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Octal Registered Transceiver with Parity and Flags

General Description The 74F552 octal transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock pulse and clock enable input as well as a flag flip-flop that is set automatically as the register is loaded. The flag output wi

文件：80.84 Kbytes 頁數(shù)：8 Pages

FAIRCHILD

仙童半導(dǎo)體

Octal Registered Transceiver with Parity and Flags

General Description The 74F552 octal transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock pulse and clock enable input as well as a flag flip-flop that is set automatically as the register is loaded. The flag output wi

文件：80.84 Kbytes 頁數(shù)：8 Pages

FAIRCHILD

仙童半導(dǎo)體