Octal registered transceiver, non-inverting 3-State

DESCRIPTION The 74F543 and 74F544 Octal Registered Transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of in

文件：119.39 Kbytes 頁數(shù)：16 Pages

PHI

PHI

Octal latched transceiver with dual enable; 3-state

General description The 74F543 octal latched transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch enable (LEAB, LEBA) and output enable (OEAB, OEBA) inputs are provided for each register to permit independent control of data t

文件：99.26 Kbytes 頁數(shù)：15 Pages

恩XP

Octal latched transceiver with dual enable; 3-state

General description The 74F543 octal latched transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch enable (LEAB, LEBA) and output enable (OEAB, OEBA) inputs are provided for each register to permit independent control of data t

文件：99.26 Kbytes 頁數(shù)：15 Pages

恩XP

Octal registered transceiver, non-inverting 3-State

恩XP

Octal registered transceiver, non-inverting (3-State)

DESCRIPTION\nThe 74F543 Octal Registered Transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of inputting and o ? Combines74F245 and 74F373 type functions in one chip\n? 8-bit octal transceiver with D-type latch\n? Back-to-back registers for storage\n? Separate controls for data flow in each direction\n? A outputs sink 20 mA and source 3 mA\n? B outputs sink 64 mA and source 15 mA\n? 3-State outputs for bus-o;

恩XP