Dual D-type flip-flop

DESCRIPTION The 74F74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are in

文件：80.55 Kbytes 頁數(shù)：8 Pages

PHI

PHI

Dual D-type flip-flop

FEATURE ? Industrial temperature range available (–40°C to +85°C) DESCRIPTION The 74F74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs

文件：209.49 Kbytes 頁數(shù)：9 Pages

NEXPERIA

安世

Dual D-type flip-flop

FEATURE ? Industrial temperature range available (–40°C to +85°C) DESCRIPTION The 74F74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs

文件：209.49 Kbytes 頁數(shù)：9 Pages

NEXPERIA

安世

Dual D-type flip-flop

DESCRIPTION The 74F74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are in

文件：80.55 Kbytes 頁數(shù)：8 Pages

PHI

PHI

Dual D-type flip-flop

The 74F74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are inactive (high),

Nexperia

安世

Dual D-type flip-flop

恩XP

IC FF D-TYPE DUAL 1BIT 14DIP

恩XP

Package：14-SOIC（0.154"，3.90mm 寬）；包裝：管件 功能：設(shè)置（預(yù)設(shè)）和復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE DUAL 1BIT 14SO

Nexperia USA Inc.