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    首頁 >N74F2953D>規(guī)格書列表

    型號下載 訂購功能描述制造商 上傳企業(yè)LOGO

    N74F2953D

    Registered transceiver, non-inverting 3-State

    DESCRIPTION The 74F2952 and 74F2953 are 8-bit registered transceivers. Two 8-bit back-to-back registers store data flowing in both directions between two bi-directional buses. Data applied to the inputs is entered and stored on the rising edge of the Clock (CPXX) provided that the Clock Enable (C

    文件:142.74 Kbytes 頁數(shù):14 Pages

    PHI

    PHI

    PHI

    N74F2953N

    Registered transceiver, non-inverting 3-State

    DESCRIPTION The 74F2952 and 74F2953 are 8-bit registered transceivers. Two 8-bit back-to-back registers store data flowing in both directions between two bi-directional buses. Data applied to the inputs is entered and stored on the rising edge of the Clock (CPXX) provided that the Clock Enable (C

    文件:142.74 Kbytes 頁數(shù):14 Pages

    PHI

    PHI

    PHI

    74F2953

    Registered transceiver, non-inverting 3-State

    DESCRIPTION The 74F2952 and 74F2953 are 8-bit registered transceivers. Two 8-bit back-to-back registers store data flowing in both directions between two bi-directional buses. Data applied to the inputs is entered and stored on the rising edge of the Clock (CPXX) provided that the Clock Enable (C

    文件:142.74 Kbytes 頁數(shù):14 Pages

    PHI

    PHI

    PHI

    N74F2953A

    Registered transceiver, non-inverting 3-State

    DESCRIPTION The 74F2952 and 74F2953 are 8-bit registered transceivers. Two 8-bit back-to-back registers store data flowing in both directions between two bi-directional buses. Data applied to the inputs is entered and stored on the rising edge of the Clock (CPXX) provided that the Clock Enable (C

    文件:142.74 Kbytes 頁數(shù):14 Pages

    PHI

    PHI

    PHI

    詳細(xì)參數(shù)

    • 型號:

      N74F2953D

    • 功能描述:

      Single 8-Bit Inverting Bus Transceiver

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    更多N74F2953D供應(yīng)商 更新時(shí)間2026-1-22 18:30:00

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