Registered transceiver, non-inverting 3-State

DESCRIPTION The 74F2952 and 74F2953 are 8-bit registered transceivers. Two 8-bit back-to-back registers store data flowing in both directions between two bi-directional buses. Data applied to the inputs is entered and stored on the rising edge of the Clock (CPXX) provided that the Clock Enable (C

文件：142.74 Kbytes 頁(yè)數(shù)：14 Pages

PHI

PHI

Registered transceiver, non-inverting 3-State

DESCRIPTION The 74F2952 and 74F2953 are 8-bit registered transceivers. Two 8-bit back-to-back registers store data flowing in both directions between two bi-directional buses. Data applied to the inputs is entered and stored on the rising edge of the Clock (CPXX) provided that the Clock Enable (C

文件：142.74 Kbytes 頁(yè)數(shù)：14 Pages

PHI

PHI

Registered transceiver, non-inverting 3-State

DESCRIPTION The 74F2952 and 74F2953 are 8-bit registered transceivers. Two 8-bit back-to-back registers store data flowing in both directions between two bi-directional buses. Data applied to the inputs is entered and stored on the rising edge of the Clock (CPXX) provided that the Clock Enable (C

文件：142.74 Kbytes 頁(yè)數(shù)：14 Pages

PHI

PHI

Registered transceiver, non-inverting 3-State

DESCRIPTION The 74F2952 and 74F2953 are 8-bit registered transceivers. Two 8-bit back-to-back registers store data flowing in both directions between two bi-directional buses. Data applied to the inputs is entered and stored on the rising edge of the Clock (CPXX) provided that the Clock Enable (C

文件：142.74 Kbytes 頁(yè)數(shù)：14 Pages

PHI

PHI