Global Digital Trunk Synchronizer

Description The MT9042 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.

文件：122.3 Kbytes 頁數(shù)：16 Pages

MITEL

Global Digital Trunk Synchronizer

Description\nThe MT9042 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.544 ? Provides T1 and E1 clocks, and ST-BUS/GCI framing signals locked to an input reference of either 8 kHz (frame pulse), 1.544 MHz (T1), or 2.048 MHz (E1)\n? Meets AT & T TR62411 and ETSI ETS 300 011 specifications for a 1.544 MHz (T1), or 2.048 MHz (E1) input reference\n? Provides Time Interval Erro;

Mitel

Multitrunk System Synchronizer

The MT9042C Multitrunk System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9042C generates ST-BUS clock and framing signals that are phase locked to either a 2.048 MHz, 1.54 ? Meets jitter requirements for: AT&T TR62411 Stratum 3, 4 and Stratum 4 Enhanced for DS1 interfaces; and for ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 for E1 interfaces\n? Provides C1.5, C3, C2, C4, C8 and C16 output clock signals\n? Provides 8 kHz ST-BUS framing signals\n? Selectable 1.544 MHz, 2;

Microchip

微芯科技

Global Digital Trunk Synchronizer

Description The MT9042 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.

文件：122.3 Kbytes 頁數(shù)：16 Pages

MITEL

Multitrunk System Synchronizer

Description The MT9042C Multitrunk System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9042C generates ST-BUS clock and framing signals that are phase locked to eith

文件：113.6 Kbytes 頁數(shù)：28 Pages

MITEL

Multitrunk System Synchronizer

Description The MT9042C Multitrunk System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9042C generates ST-BUS clock and framing signals that are phase locked to eith

文件：113.6 Kbytes 頁數(shù)：28 Pages

MITEL

Multitrunk System Synchronizer

Microchip

微芯科技

Package：28-LCC（J 形引線）；包裝：托盤 功能：數(shù)字鎖相環(huán) 類別：集成電路（IC） 電信 描述：IC TELECOM INTERFACE 28PLCC

MICROCHIP

微芯科技

Package：28-LCC（J 形引線）；包裝：托盤 功能：數(shù)字鎖相環(huán) 類別：集成電路（IC） 電信 描述：IC TELECOM INTERFACE 28PLCC

MICROCHIP

微芯科技