DRAM

GENERAL DESCRIPTION The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits organized in a x16 configuration. The MT4LC4M16F5 is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in

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MICRON

美光

4 MEG x 16 FPM DRAM

GENERAL DESCRIPTION\nThe 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits organized in a x16 configuration. The MT4LC4M16F5 is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,0 ? Single +3.3V ±0.3V power supply\n? Industry-standard x16 pinout, timing, functions, and packages\n? 12 row, 10 column addresses\n? High-performance CMOS silicon-gate process\n? All inputs, outputs and clocks are LVTTL-compatible\n? FAST PAGE MODE (FPM) access\n? 4,096-cycle CAS#-BEFORE-RAS# (CBR) ;

Micron

美光

SOJ24

MICRON

美光

上傳：深圳市旺財半導(dǎo)體有限公司

TSSOP

MIC

昌福電子

上傳：深圳市勤思達科技有限公司

TSSOP

MICRON

美光

上傳：深圳市勤思達科技有限公司