3.3 V 1:12 LVCMOS PLL Clock Generator

Features ? 1:12 PLL based low-voltage clock generator ? 3.3 V power supply ? Internal power-on reset ? Generates clock signals up to 242.5 MHz ? Maximum output skew of 250 ps ? Differential PECL reference clock input ? Two LVCMOS PLL reference clock inputs ? External PLL feedback supports

文件：557.87 Kbytes 頁數(shù)：22 Pages

RENESAS

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3.3 V 1:12 LVCMOS PLL Clock Generator

文件：490.26 Kbytes 頁數(shù)：19 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導體

3.3V 1:12 LVCMOS PLL Clock Generator

The MPC9773 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9773 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedba 1:12 PLL based low-voltage clock generator\n3.3 V power supply\nInternal power-on reset\nGenerates clock signals up to 242.5 MHz\nMaximum output skew of 250 ps\nDifferential PECL reference clock input\nTwo LVCMOS PLL reference clock inputs\nExternal PLL feedback supports zero-delay capability\nVario;

Renesas

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3.3V 1:12 LVCMOS PLL Clock Generatorzer

恩XP

3.3 V 1:12 LVCMOS PLL Clock Generator

文件：490.26 Kbytes 頁數(shù)：19 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導體

3.3 V 1:12 LVCMOS PLL Clock Generator

文件：490.26 Kbytes 頁數(shù)：19 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導體

Package：52-LQFP；包裝：卷帶（TR） 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC PLL CLK GEN 1:12 3.3V 52-LQFP

Renesas Electronics America Inc

Package：52-LQFP；包裝：卷帶（TR） 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC PLL CLK GEN 1:12 3.3V 52-LQFP

Renesas Electronics America Inc