CMOS MSI Quad R?? Latches

文件：118.43 Kbytes 頁數(shù)：7 Pages

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CMOS MSI Quad R?? Latches

文件：143.25 Kbytes 頁數(shù)：7 Pages

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CMOS MSI Quad R?? Latches

文件：104.25 Kbytes 頁數(shù)：8 Pages

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安森美半導(dǎo)體

CMOS MSI Quad R?? Latches

文件：118.43 Kbytes 頁數(shù)：7 Pages

ONSEMI

安森美半導(dǎo)體

CMOS MSI Quad R?? Latches

文件：143.25 Kbytes 頁數(shù)：7 Pages

ONSEMI

安森美半導(dǎo)體

四路 R-S 鎖存

The MC14043B and MC14044B quad R-S latches are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. Th ? Double Diode Input Protection\n? Three-State Outputs with Common Enable\n? Outputs Capable of Driving Two Low-power TTL Loads or One Low-Power Schottky TTL Load Over the Rated Temperature Range\n? Supply Voltage Range = 3.0 Vdc to 18 Vdc\n? Pb-Free Packages are Available*;

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Quad R–S Latches

The MC14043B and MC14044B quad R–S latches are constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three–state buffers having a common enable input. Th

恩XP

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR）剪切帶（CT） 類別：集成電路（IC） 鎖存器 描述：IC LATCH R-S QUAD NOR 16SOIC

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Package：16-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 鎖存器 描述：IC LATCH R-S QUAD NOR 16SOIC

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Package：16-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 鎖存器 描述：IC LATCH R-S QUAD P/N 16-SOIC

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安森美半導(dǎo)體