1152 x 8-BIT LINE MEMORY FIFO

DESCRIPTION The M66252P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 1152-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read and is most suitable as a buff

文件：145.77 Kbytes 頁(yè)數(shù)：11 Pages

MITSUBISHI

三菱電機(jī)

1152*8-BIT LINE MEMORY(FIFO)

DESCRIPTION The M66252P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 1152-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read and is most suitable as a buff

文件：2.19838 Mbytes 頁(yè)數(shù)：12 Pages

RENESAS

瑞薩

Low input current requirement: 0.5mA

文件：68.52 Kbytes 頁(yè)數(shù)：2 Pages

MICROPAC

N-Channel 25 V (D-S) MOSFET

FEATURES ? 100 Rg and UIS Tested ? DT-Trench Power MOSFET APPLICATIONS ? High power density DC/DC ? Load switching ? Battery management

文件：639.11 Kbytes 頁(yè)數(shù)：7 Pages

DINTEK

尚鼎芯

1152*8-BIT LINE MEMORY(FIFO)

DESCRIPTION The M66252P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 1152-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read and is most suitable as a buff

文件：2.19838 Mbytes 頁(yè)數(shù)：12 Pages

RENESAS

瑞薩