5120 x 8-BIT x 2 LINE MEMORY

DESCRIPTION The M66281FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 5120 words x 8 bits x 2. Since memory is available to simultaneously output 1 line delay and 2 line delay data, the

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MITSUBISHI

三菱電機(jī)

5120 ? 8-Bit ? 2 Line Memory

Description The M66281FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 5120 words × 8 bits × 2. Since memory is available to simultaneously output 1 line delay and 2 line delay data, the

文件：175.66 Kbytes 頁數(shù)：16 Pages

RENESAS

瑞薩

5120 × 8-Bit × 2 Line Memory

Renesas

瑞薩

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