DDR SDRAM SODIMM

Feature ? Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? Programmable Read latency 2, 2.5 (c

文件：264.46 Kbytes 頁數(shù)：20 Pages

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DDR SDRAM SODIMM

Feature ? Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? Programmable Read latency 2, 2.5 (c

文件：264.46 Kbytes 頁數(shù)：20 Pages

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DDR SDRAM SODIMM

Feature ? Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? Programmable Read latency 2, 2.5 (c

文件：264.46 Kbytes 頁數(shù)：20 Pages

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DDR SDRAM Product Guide

Consumer Memory

文件：239 Kbytes 頁數(shù)：10 Pages

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DDR SDRAM Product Guide

Consumer Memory

文件：239 Kbytes 頁數(shù)：10 Pages

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512MB Unbuffered SODIMM(based on sTSOP)

Feature ? Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? Programmable Read latency 2, 2.5 (c

文件：145.93 Kbytes 頁數(shù)：13 Pages

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512MB Unbuffered SODIMM(based on sTSOP)

Feature ? Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? Programmable Read latency 2, 2.5 (c

文件：145.93 Kbytes 頁數(shù)：13 Pages

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512MB Unbuffered SODIMM(based on sTSOP)

Feature ? Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? Programmable Read latency 2, 2.5 (c

文件：145.93 Kbytes 頁數(shù)：13 Pages

SAMSUNG

三星

512MB Unbuffered SODIMM(based on sTSOP)

Feature ? Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? Programmable Read latency 2, 2.5 (c

文件：145.93 Kbytes 頁數(shù)：13 Pages

SAMSUNG

三星

512MB Unbuffered SODIMM(based on sTSOP)

Feature ? Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? Programmable Read latency 2, 2.5 (c

文件：145.93 Kbytes 頁數(shù)：13 Pages

SAMSUNG

三星