絲?。?strong>LV8；Package：UJ-5；20 V, 200 mA, Low Noise, CMOS LDO Linear Regulator

GENERAL DESCRIPTION The ADP7118 is a CMOS, low dropout (LDO) linear regulator that operates from 2.7 V to 20 V and provides up to 200 mA of output current. This high input voltage LDO is ideal for the regulation of high performance analog and mixed-signal circuits operating from 20 V down to 1.2

文件：915.43 Kbytes 頁數：24 Pages

AD

亞德諾

絲印：LV810RILF；Package：QSOP；BUFFER/CLOCK DRIVER

Features ? Packaged in 20-pin QSOP/SSOP ? Split 1:10 fanout Buffer ? Maximum skew between outputs of different packages 0.75 ns ? Max propagation delay of 3.8 ns ? Operating voltage of 1.5 V to 2.5 V on Bank A ? Operating voltage of 1.5 V to 2.5 V on Banks B and C ? Advanced, low power, CM

文件：479.97 Kbytes 頁數：15 Pages

RENESAS

瑞薩

絲?。?a target="_blank" title="Marking" href="/lv810rilf/marking.html">LV810RILF；Package：QSOP；BUFFER/CLOCK DRIVER

Features ? Packaged in 20-pin QSOP/SSOP ? Split 1:10 fanout Buffer ? Maximum skew between outputs of different packages 0.75 ns ? Max propagation delay of 3.8 ns ? Operating voltage of 1.5 V to 2.5 V on Bank A ? Operating voltage of 1.5 V to 2.5 V on Banks B and C ? Advanced, low power, CM

文件：479.97 Kbytes 頁數：15 Pages

RENESAS

瑞薩

絲?。?a target="_blank" title="Marking" href="/lv810rilf/marking.html">LV810RILF；Package：QSOP；BUFFER/CLOCK DRIVER

Features ? Packaged in 20-pin QSOP/SSOP ? Split 1:10 fanout Buffer ? Maximum skew between outputs of different packages 0.75 ns ? Max propagation delay of 3.8 ns ? Operating voltage of 1.5 V to 2.5 V on Bank A ? Operating voltage of 1.5 V to 2.5 V on Banks B and C ? Advanced, low power, CM

文件：479.97 Kbytes 頁數：15 Pages

RENESAS

瑞薩

絲?。?a target="_blank" title="Marking" href="/lv810rilf/marking.html">LV810RILF；Package：QSOP；BUFFER/CLOCK DRIVER

Features ? Packaged in 20-pin QSOP/SSOP ? Split 1:10 fanout Buffer ? Maximum skew between outputs of different packages 0.75 ns ? Max propagation delay of 3.8 ns ? Operating voltage of 1.5 V to 2.5 V on Bank A ? Operating voltage of 1.5 V to 2.5 V on Banks B and C ? Advanced, low power, CM

文件：479.97 Kbytes 頁數：15 Pages

RENESAS

瑞薩

絲印：LV8151；Package：TVSOP；10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS

2-V to 5.5-V VCC Operation Max tpd of 15 ns at 5 V Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time Polarity Control for Y Outputs Selects True or Complementary Logic Typical VOLP (Output Ground Bounce) 2.3 V

文件：569.4 Kbytes 頁數：20 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/lv8151/marking.html">LV8151；Package：TVSOP；10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS

2-V to 5.5-V VCC Operation Max tpd of 15 ns at 5 V Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time Polarity Control for Y Outputs Selects True or Complementary Logic Typical VOLP (Output Ground Bounce) 2.3 V

文件：569.4 Kbytes 頁數：20 Pages

TI

德州儀器

絲印：LV8151；Package：SOIC；10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS

2-V to 5.5-V VCC Operation Max tpd of 15 ns at 5 V Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time Polarity Control for Y Outputs Selects True or Complementary Logic Typical VOLP (Output Ground Bounce) 2.3 V

文件：569.4 Kbytes 頁數：20 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/lv8151/marking.html">LV8151；Package：SOIC；10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS

2-V to 5.5-V VCC Operation Max tpd of 15 ns at 5 V Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time Polarity Control for Y Outputs Selects True or Complementary Logic Typical VOLP (Output Ground Bounce) 2.3 V

文件：569.4 Kbytes 頁數：20 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/lv8151/marking.html">LV8151；Package：SOIC；10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS

2-V to 5.5-V VCC Operation Max tpd of 15 ns at 5 V Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time Polarity Control for Y Outputs Selects True or Complementary Logic Typical VOLP (Output Ground Bounce) 2.3 V

文件：569.4 Kbytes 頁數：20 Pages

TI

德州儀器