| 型號(hào) | 下載 訂購(gòu) | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
絲印：LV8；Package：UJ-5；20 V, 200 mA, Low Noise, CMOS LDO Linear Regulator GENERAL DESCRIPTION The ADP7118 is a CMOS, low dropout (LDO) linear regulator that operates from 2.7 V to 20 V and provides up to 200 mA of output current. This high input voltage LDO is ideal for the regulation of high performance analog and mixed-signal circuits operating from 20 V down to 1.2 文件：915.43 Kbytes 頁(yè)數(shù)：24 Pages | AD 亞德諾 | AD | ||
絲?。?a target="_blank" title="Marking" href="/lv810rilf/marking.html">LV810RILF；Package：QSOP；BUFFER/CLOCK DRIVER Features ? Packaged in 20-pin QSOP/SSOP ? Split 1:10 fanout Buffer ? Maximum skew between outputs of different packages 0.75 ns ? Max propagation delay of 3.8 ns ? Operating voltage of 1.5 V to 2.5 V on Bank A ? Operating voltage of 1.5 V to 2.5 V on Banks B and C ? Advanced, low power, CM 文件：479.97 Kbytes 頁(yè)數(shù)：15 Pages | RENESAS 瑞薩 | RENESAS | ||
絲印：LV810RILF；Package：QSOP；BUFFER/CLOCK DRIVER Features ? Packaged in 20-pin QSOP/SSOP ? Split 1:10 fanout Buffer ? Maximum skew between outputs of different packages 0.75 ns ? Max propagation delay of 3.8 ns ? Operating voltage of 1.5 V to 2.5 V on Bank A ? Operating voltage of 1.5 V to 2.5 V on Banks B and C ? Advanced, low power, CM 文件：479.97 Kbytes 頁(yè)數(shù)：15 Pages | RENESAS 瑞薩 | RENESAS | ||
絲印：LV810RILF；Package：QSOP；BUFFER/CLOCK DRIVER Features ? Packaged in 20-pin QSOP/SSOP ? Split 1:10 fanout Buffer ? Maximum skew between outputs of different packages 0.75 ns ? Max propagation delay of 3.8 ns ? Operating voltage of 1.5 V to 2.5 V on Bank A ? Operating voltage of 1.5 V to 2.5 V on Banks B and C ? Advanced, low power, CM 文件：479.97 Kbytes 頁(yè)數(shù)：15 Pages | RENESAS 瑞薩 | RENESAS | ||
絲?。?a target="_blank" title="Marking" href="/lv810rilf/marking.html">LV810RILF；Package：QSOP；BUFFER/CLOCK DRIVER Features ? Packaged in 20-pin QSOP/SSOP ? Split 1:10 fanout Buffer ? Maximum skew between outputs of different packages 0.75 ns ? Max propagation delay of 3.8 ns ? Operating voltage of 1.5 V to 2.5 V on Bank A ? Operating voltage of 1.5 V to 2.5 V on Banks B and C ? Advanced, low power, CM 文件：479.97 Kbytes 頁(yè)數(shù)：15 Pages | RENESAS 瑞薩 | RENESAS | ||
絲?。?a target="_blank" title="Marking" href="/lv8151/marking.html">LV8151；Package：TVSOP；10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS 2-V to 5.5-V VCC Operation Max tpd of 15 ns at 5 V Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time Polarity Control for Y Outputs Selects True or Complementary Logic Typical VOLP (Output Ground Bounce) 2.3 V 文件：569.4 Kbytes 頁(yè)數(shù)：20 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/lv8151/marking.html">LV8151；Package：TVSOP；10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS 2-V to 5.5-V VCC Operation Max tpd of 15 ns at 5 V Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time Polarity Control for Y Outputs Selects True or Complementary Logic Typical VOLP (Output Ground Bounce) 2.3 V 文件：569.4 Kbytes 頁(yè)數(shù)：20 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/lv8151/marking.html">LV8151；Package：SOIC；10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS 2-V to 5.5-V VCC Operation Max tpd of 15 ns at 5 V Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time Polarity Control for Y Outputs Selects True or Complementary Logic Typical VOLP (Output Ground Bounce) 2.3 V 文件：569.4 Kbytes 頁(yè)數(shù)：20 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/lv8151/marking.html">LV8151；Package：SOIC；10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS 2-V to 5.5-V VCC Operation Max tpd of 15 ns at 5 V Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time Polarity Control for Y Outputs Selects True or Complementary Logic Typical VOLP (Output Ground Bounce) 2.3 V 文件：569.4 Kbytes 頁(yè)數(shù)：20 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/lv8151/marking.html">LV8151；Package：SOIC；10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS 2-V to 5.5-V VCC Operation Max tpd of 15 ns at 5 V Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time Polarity Control for Y Outputs Selects True or Complementary Logic Typical VOLP (Output Ground Bounce) 2.3 V 文件：569.4 Kbytes 頁(yè)數(shù)：20 Pages | TI 德州儀器 | TI |
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
ADI(亞德諾) |
25+ |
標(biāo)準(zhǔn)封裝 |
11663 |
我們只是原廠的搬運(yùn)工 |
詢價(jià) | ||
ADI |
25+ |
SMD |
518000 |
明嘉萊只做原裝正品現(xiàn)貨 |
詢價(jià) | ||
ADI/亞德諾 |
25+ |
SOT23-5 |
20000 |
原裝正品現(xiàn)貨支持實(shí)單 |
詢價(jià) | ||
ADI(亞德諾) |
2511 |
TSOT-23-5 |
9850 |
電子元器件采購(gòu)降本 30%!公司原廠直采,砍掉中間差價(jià) |
詢價(jià) | ||
ADI |
2432+ |
3200 |
訂貨在途 實(shí)單價(jià)優(yōu) |
詢價(jià) | |||
ADI/亞德諾 |
21+ |
SOT23-5 |
20000 |
優(yōu)勢(shì)供應(yīng) 實(shí)單必成 可開(kāi)13點(diǎn)增值稅 |
詢價(jià) | ||
ADI(亞德諾) |
23+ |
NA |
20094 |
正納10年以上分銷經(jīng)驗(yàn)原裝進(jìn)口正品做服務(wù)做口碑有支持 |
詢價(jià) | ||
ADI |
23+ |
SOT23 |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價(jià) | ||
ADI |
20+ |
SOT23 |
9212 |
一級(jí)代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力 |
詢價(jià) | ||
ADI(亞德諾) |
23+ |
N/A |
10000 |
正規(guī)渠道,只有原裝! |
詢價(jià) |
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