PRELIMINARY INFORMATION PLL Clock Divider

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on

文件：59.89 Kbytes 頁(yè)數(shù)：4 Pages

ICST

PLL Clock Divider

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on th ? Packaged in 8 pin SOIC\n? Low cost clock divider\n? Low skew (500ps) outputs. One is ÷ 2 of other.\n? Easy to use with other generators and buffers\n? Input clock frequency up to 135 MHz at 3.3 V\n? Input clock frequency up to 156 MHz at 5.0 V\n? Tolerant of poor input clock duty cycle, jitter.\n?;

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瑞薩

PRELIMINARY INFORMATION PLL Clock Divider

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on

文件：59.89 Kbytes 頁(yè)數(shù)：4 Pages

ICST

PRELIMINARY INFORMATION PLL Clock Divider

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on

文件：59.89 Kbytes 頁(yè)數(shù)：4 Pages

ICST

絲?。?a target="_blank" title="Marking" href="/ics54110ail/marking.html">ICS54110AIL；Package：VFQFN；2.5V Differential LVDS Clock Buffer

General Description The ICS854110I is a high-performance differential LVDS clock fanout buffer. The device is designed for signal fanout of high-frequency, low phase-noise clock signals. The selected differential input signal is distributed to ten differential LVDS outputs. The ICS854110I is char

文件：851.22 Kbytes 頁(yè)數(shù)：21 Pages

IDT

絲印：ICS54110AIL；Package：VFQFN；2.5V Differential LVDS Clock Buffer

General Description The ICS854110I is a high-performance differential LVDS clock fanout buffer. The device is designed for signal fanout of high-frequency, low phase-noise clock signals. The selected differential input signal is distributed to ten differential LVDS outputs. The ICS854110I is char

文件：851.22 Kbytes 頁(yè)數(shù)：21 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/ics54110ail/marking.html">ICS54110AIL；Package：LQFP；2.5V Differential LVDS Clock Buffer

General Description The ICS854110I is a high-performance differential LVDS clock fanout buffer. The device is designed for signal fanout of high-frequency, low phase-noise clock signals. The selected differential input signal is distributed to ten differential LVDS outputs. The ICS854110I is char

文件：851.22 Kbytes 頁(yè)數(shù)：21 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/ics54110ail/marking.html">ICS54110AIL；Package：LQFP；2.5V Differential LVDS Clock Buffer

General Description The ICS854110I is a high-performance differential LVDS clock fanout buffer. The device is designed for signal fanout of high-frequency, low phase-noise clock signals. The selected differential input signal is distributed to ten differential LVDS outputs. The ICS854110I is char

文件：851.22 Kbytes 頁(yè)數(shù)：21 Pages

IDT