PRELIMINARY INFORMATION Clock Divider and 2X Multiplier

Description The ICS543 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 90 MHz at 5.0 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 3, 5, 6, or 10, or a multiply by 2 of the input

文件：60.37 Kbytes 頁數(shù)：4 Pages

ICST

PRELIMINARY INFORMATION Clock Divider and 2X Multiplier

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PRELIMINARY INFORMATION Clock Divider and 2X Multiplier

Description The ICS543 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 90 MHz at 5.0 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 3, 5, 6, or 10, or a multiply by 2 of the input

文件：60.37 Kbytes 頁數(shù)：4 Pages

ICST

PRELIMINARY INFORMATION Clock Divider and 2X Multiplier

Description The ICS543 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 90 MHz at 5.0 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 3, 5, 6, or 10, or a multiply by 2 of the input

文件：60.37 Kbytes 頁數(shù)：4 Pages

ICST