Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

文件：64.81 Kbytes 頁數(shù)：7 Pages

PHI

PHI

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

文件：64.81 Kbytes 頁數(shù)：7 Pages

PHI

PHI

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

文件：64.81 Kbytes 頁數(shù)：7 Pages

PHI

PHI

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

文件：64.81 Kbytes 頁數(shù)：7 Pages

PHI

PHI