Dual 4-bit latch

DESCRIPTION The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe (ST), master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outp

文件：107.27 Kbytes 頁數：9 Pages

PHI

PHI

Dual 4-bit latch

DESCRIPTION The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe (ST), master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outp

文件：107.27 Kbytes 頁數：9 Pages

PHI

PHI

Dual 4-bit latch

DESCRIPTION The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe (ST), master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outp

文件：107.27 Kbytes 頁數：9 Pages

PHI

PHI

Dual 4-bit latch

DESCRIPTION The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe (ST), master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outp

文件：107.27 Kbytes 頁數：9 Pages

PHI

PHI