Synchronous up/down counter, binary/decade counter

DESCRIPTION The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input

文件：188.66 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Synchronous up/down counter, binary/decade counter

DESCRIPTION The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input

文件：188.66 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Synchronous up/down counter, binary/decade counter

DESCRIPTION The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input

文件：188.66 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Synchronous up/down counter, binary/decade counter

DESCRIPTION The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input

文件：188.66 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Synchronous up/down counter, binary/decade counter

DESCRIPTION The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input

文件：188.66 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Synchronous up/down counter, binary/decade counter

DESCRIPTION The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input

文件：188.66 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Synchronous up/down counter, binary/decade counter

DESCRIPTION The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input

文件：188.66 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Synchronous up/down counter, binary/decade counter

DESCRIPTION\nThe HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input (PL)

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Synchronous up/down counter, binary/decade counter

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