Tolerant of slow clock rise and fall times

文件：108.33 Kbytes 頁數(shù)：15 Pages

恩XP

Tolerant of slow clock rise and fall times

文件：108.33 Kbytes 頁數(shù)：15 Pages

恩XP

Dual 4-bit static shift register

恩XP

Dual 4-bit static shift register

General description\nThe HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (MR). Informat

恩XP

Dual 4-bit static shift register

The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (MR). Information present on D is s ? Tolerant of slow clock rise and fall times\n? Fully static operation\n? 5 V, 10 V, and 15 V parametric ratings\n? Standardized symmetrical output characteristics\n? Specified from -40 °C to +85 °C.\n? Complies with JEDEC standard JESD 13-B;

Nexperia

安世

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：管件 功能：串行至并行 類別：集成電路（IC） 移位寄存器 描述：IC REGISTER STATIC 4BIT 16-SOIC

Nexperia USA Inc.

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：管件 功能：串行至并行 類別：集成電路（IC） 移位寄存器 描述：IC STATIC SHIFT REG 4BIT 16SOIC

Nexperia USA Inc.