| 型號(hào) | 下載 訂購 | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
HD74AC74 | Dual D-Type Positive Edge-Triggered Flip-Flop Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not dir 文件:61.42 Kbytes 頁數(shù):10 Pages | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | |
HD74AC74 | Dual D-Type Positive Edge-Triggered Flip-Flop Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not dir 文件:121.33 Kbytes 頁數(shù):8 Pages | RENESAS 瑞薩 | RENESAS | |
HD74AC74 | Standard IC>General-Purpose Logics>HD74AC Series | Renesas 瑞薩 | Renesas | |
Dual D-Type Positive Edge-Triggered Flip-Flop Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not dir 文件:121.33 Kbytes 頁數(shù):8 Pages | RENESAS 瑞薩 | RENESAS | ||
Dual D-Type Positive Edge-Triggered Flip-Flop Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not dir 文件:121.33 Kbytes 頁數(shù):8 Pages | RENESAS 瑞薩 | RENESAS | ||
Dual D-Type Positive Edge-Triggered Flip-Flop Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not dir 文件:121.33 Kbytes 頁數(shù):8 Pages | RENESAS 瑞薩 | RENESAS | ||
Dual D-Type Positive Edge-Triggered Flip-Flop Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not dir 文件:121.33 Kbytes 頁數(shù):8 Pages | RENESAS 瑞薩 | RENESAS | ||
General-Purpose Logics-HD74AC Series | Renesas 瑞薩 | Renesas | ||
General-Purpose Logics-HD74AC Series | Renesas 瑞薩 | Renesas |
技術(shù)參數(shù)
- Family.:
HD74AC Series
- Function Gr1:
Latch/Flip-Flop/Register
- Function Gr2:
D type FlipFlop
- Function:
Dual D-type Flip-Flops with Preset and Clear
- Number of Channel:
2
- Topa[Tjopa] (degC) min.:
-40
- Topa[Tjopa] (degC) max.:
85
- Vcc (V) min.:
2
- Vcc (V) max.:
6.0
- Iout (mA):
±24
- Propagation Delay (ns) max.:
10.5
- Package Type:
SOP
- Production Status:
Non-promotion
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
HIT/SOP5.2 |
23+ |
52397 |
##公司主營品牌長期供應(yīng)100%原裝現(xiàn)貨可含稅提供技術(shù) |
詢價(jià) | |||
HIT |
2015+ |
SOP14 |
19889 |
一級(jí)代理原裝現(xiàn)貨,特價(jià)熱賣! |
詢價(jià) | ||
HIT |
23+ |
SOP |
7000 |
絕對(duì)全新原裝!100%保質(zhì)量特價(jià)!請(qǐng)放心訂購! |
詢價(jià) | ||
HIT |
24+ |
SOP |
2000 |
詢價(jià) | |||
HIT |
04+ |
SOP-14 |
4 |
原裝現(xiàn)貨海量庫存歡迎咨詢 |
詢價(jià) | ||
HIT |
22+ |
SOP |
1148 |
全新原裝現(xiàn)貨!自家?guī)齑? |
詢價(jià) | ||
HIT |
25+ |
SOP |
2987 |
只售原裝自家現(xiàn)貨!誠信經(jīng)營!歡迎來電! |
詢價(jià) | ||
HIT |
24+ |
SOP14 |
20000 |
全新原廠原裝,進(jìn)口正品現(xiàn)貨,正規(guī)渠道可含稅??! |
詢價(jià) | ||
HITACHI |
20+ |
SOP-14 |
2960 |
誠信交易大量庫存現(xiàn)貨 |
詢價(jià) | ||
RENESAS/瑞薩 |
25+ |
SOP14 |
9800 |
全新原裝現(xiàn)貨,假一賠十 |
詢價(jià) |
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