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首頁(yè) >HD74AC>規(guī)格書列表

型號(hào)	下載訂購(gòu)	功能描述	制造商上傳企業(yè)	LOGO
HD74AC112	文件：240.9 Kbytes Page：10 Pages	Dual JK Negative Edge-Triggered Flip-Flop Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will 文件：240.9 Kbytes 頁(yè)數(shù)：10 Pages	RENESAS 瑞薩	RENESAS
HD74AC112FPEL	文件：240.9 Kbytes Page：10 Pages	Dual JK Negative Edge-Triggered Flip-Flop Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will 文件：240.9 Kbytes 頁(yè)數(shù)：10 Pages	RENESAS 瑞薩	RENESAS
HD74AC112RPEL	文件：240.9 Kbytes Page：10 Pages	Dual JK Negative Edge-Triggered Flip-Flop Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will 文件：240.9 Kbytes 頁(yè)數(shù)：10 Pages	RENESAS 瑞薩	RENESAS
HD74AC123A	文件：50.18 Kbytes Page：9 Pages	Dual Retriggerable Resettable Multivibrator Description Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth Table) will cause the delay period to start again, wi 文件：50.18 Kbytes 頁(yè)數(shù)：9 Pages	HITACHIHitachi Semiconductor 日立日立公司	HITACHI
HD74AC123A	文件：249.38 Kbytes Page：7 Pages	Dual Retriggerable Resettable Multivibrator Description Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth Table) will cause the delay period to start again, 文件：249.38 Kbytes 頁(yè)數(shù)：7 Pages	RENESAS 瑞薩	RENESAS
HD74AC123AFPEL	文件：249.38 Kbytes Page：7 Pages	Dual Retriggerable Resettable Multivibrator Description Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth Table) will cause the delay period to start again, 文件：249.38 Kbytes 頁(yè)數(shù)：7 Pages	RENESAS 瑞薩	RENESAS
HD74AC123AP	文件：249.38 Kbytes Page：7 Pages	Dual Retriggerable Resettable Multivibrator Description Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth Table) will cause the delay period to start again, 文件：249.38 Kbytes 頁(yè)數(shù)：7 Pages	RENESAS 瑞薩	RENESAS
HD74AC123ARPEL	文件：249.38 Kbytes Page：7 Pages	Dual Retriggerable Resettable Multivibrator Description Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth Table) will cause the delay period to start again, 文件：249.38 Kbytes 頁(yè)數(shù)：7 Pages	RENESAS 瑞薩	RENESAS
HD74AC125	文件：51.13 Kbytes Page：8 Pages	Quad Buffer/Line Driver with 3-State Output Description The HD74AC125/HD74ACT125 is an quad buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter/receiver which provides improved PC board density. Features ? 3-State Outputs Drive Bus Lines or Buffer Memory Addres 文件：51.13 Kbytes 頁(yè)數(shù)：8 Pages	HITACHIHitachi Semiconductor 日立日立公司	HITACHI
HD74AC125	文件：132.91 Kbytes Page：9 Pages	Quad Buffer/Line Driver with 3-State Output Description The HD74AC125/HD74ACT125 is an quad buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter/receiver which provides improved PC board density. Features ? 3-State Outputs Drive Bus Lines orBuffer Memory Address 文件：132.91 Kbytes 頁(yè)數(shù)：9 Pages	RENESAS 瑞薩	RENESAS

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技術(shù)參數(shù)

Family.：
HD74AC Series
Function Gr1：
Gate
Function Gr2：
NAND Gate
Function：
Quad. 2-input NAND Gates
Number of Channel：
4
Topa[Tjopa] (degC) min.：
-40
Topa[Tjopa] (degC) max.：
85
Vcc (V) min.：
2
Vcc (V) max.：
6.0
Iout (mA)：
±24
Propagation Delay (ns) max.：
8.5
Package Type：
SOP
Production Status：
Non-promotion

供應(yīng)商	型號(hào)	品牌	批號(hào)	封裝	庫(kù)存	備注	價(jià)格
深圳市聯(lián)世界科技有限公司	HD74AC125	HIT	24+/25+		850	原裝正品現(xiàn)貨庫(kù)存價(jià)優(yōu)	詢價(jià)
深圳市福安甌科技有限公司	HD74AC157FPTR	HITACHI	25+	SOP	1000	強(qiáng)調(diào)現(xiàn)貨,隨時(shí)查詢!	詢價(jià)
深圳市勤思達(dá)科技有限公司	HD74ACT139FPEL	HITACHI	09+	SOP16	5500	原裝無(wú)鉛,優(yōu)勢(shì)熱賣	詢價(jià)
深圳市恒創(chuàng)達(dá)實(shí)業(yè)有限公司	HD74AC04TEL	HIT	17+	TSSOP	6200	100%原裝正品現(xiàn)貨	詢價(jià)
諦輝(北京/上海/青島 )電子科技有限公司	HD74ACT374FPEL	HITACH	25+	SOP20	18000	原廠直接發(fā)貨進(jìn)口原裝	詢價(jià)
深圳市毅創(chuàng)騰電子科技有限公司	HD74AC00FP	HIT	23+	SOP	7000	絕對(duì)全新原裝!100%保質(zhì)量特價(jià)!請(qǐng)放心訂購(gòu)!	詢價(jià)
深圳市歐立現(xiàn)代科技有限公司	HD74ACT166FP	HITACHI	24+	SOP	6980	原裝現(xiàn)貨,可開13%稅票	詢價(jià)
深圳市凌旭科技有限公司	HD74AC139FPEL	RENESAS	2016+	SOP	3000	只做原裝,假一罰十,公司可開17%增值稅發(fā)票!	詢價(jià)
芯有半導(dǎo)體（深圳）有限公司	HD74ACT139FPEL	HITACHI	00/01+	SOP16	670	全新原裝100真實(shí)現(xiàn)貨供應(yīng)	詢價(jià)
深圳市福田區(qū)綠盛電子商行	HD74AC280FP	HIT	2015+	SOP14	19889	一級(jí)代理原裝現(xiàn)貨,特價(jià)熱賣!	詢價(jià)

更多HD74AC供應(yīng)商更新時(shí)間2026-1-17 14:30:00

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